c-my 94b52f981d add shl&shr

2018-07-11 11:18:16 +08:00

.qsys_edit

initial commit

2018-07-11 00:51:22 +08:00

db

add shl&shr

2018-07-11 11:18:16 +08:00

greybox_tmp

initial commit

2018-07-11 00:51:22 +08:00

incremental_db

add shl&shr

2018-07-11 11:18:16 +08:00

output_files

add shl&shr

2018-07-11 11:18:16 +08:00

simulation

add shl&shr

2018-07-11 11:18:16 +08:00

8bit_model_nativelink_simulation.rpt

initial commit

2018-07-11 00:51:22 +08:00

8bit_model.qpf

initial commit

2018-07-11 00:51:22 +08:00

8bit_model.qsf

add shl&shr

2018-07-11 11:18:16 +08:00

8bit_model.qws

add shl&shr

2018-07-11 11:18:16 +08:00

accumulator.bsf

initial commit

2018-07-11 00:51:22 +08:00

accumulator.vhd

initial commit

2018-07-11 00:51:22 +08:00

accumulator.vhd.bak

initial commit

2018-07-11 00:51:22 +08:00

alu.bsf

add shl&shr

2018-07-11 11:18:16 +08:00

alu.vhd

add shl&shr

2018-07-11 11:18:16 +08:00

alu.vhd.bak

initial commit

2018-07-11 00:51:22 +08:00

alu.vwf

initial commit

2018-07-11 00:51:22 +08:00

ar.bsf

initial commit

2018-07-11 00:51:22 +08:00

ar.vhd

initial commit

2018-07-11 00:51:22 +08:00

ar.vhd.bak

initial commit

2018-07-11 00:51:22 +08:00

code.hex

add shl&shr

2018-07-11 11:18:16 +08:00

controller.bsf

add shl&shr

2018-07-11 11:18:16 +08:00

controller.vhd

add shl&shr

2018-07-11 11:18:16 +08:00

controller.vhd.bak

initial commit

2018-07-11 00:51:22 +08:00

dr.bsf

initial commit

2018-07-11 00:51:22 +08:00

dr.vhd

initial commit

2018-07-11 00:51:22 +08:00

dr.vhd.bak

initial commit

2018-07-11 00:51:22 +08:00

eight_bit_model.bdf

add shl&shr

2018-07-11 11:18:16 +08:00

ir.bsf

add shl&shr

2018-07-11 11:18:16 +08:00

ir.vhd

add shl&shr

2018-07-11 11:18:16 +08:00

ir.vhd.bak

initial commit

2018-07-11 00:51:22 +08:00

metronome.bsf

initial commit

2018-07-11 00:51:22 +08:00

metronome.vhd

initial commit

2018-07-11 00:51:22 +08:00

metronome.vhd.bak

initial commit

2018-07-11 00:51:22 +08:00

pc.bsf

initial commit

2018-07-11 00:51:22 +08:00

pc.vhd

initial commit

2018-07-11 00:51:22 +08:00

pc.vhd.bak

initial commit

2018-07-11 00:51:22 +08:00

ram0_inst.vhd

initial commit

2018-07-11 00:51:22 +08:00

ram0.bsf

initial commit

2018-07-11 00:51:22 +08:00

ram0.cmp

initial commit

2018-07-11 00:51:22 +08:00

ram0.qip

initial commit

2018-07-11 00:51:22 +08:00

ram0.vhd

initial commit

2018-07-11 00:51:22 +08:00

指令表.xlsx

add int table

2018-07-11 00:54:39 +08:00

S

Description

数电课设 8位模型机

12 MiB

Languages

VHDL 97.1%

Csound Document 1.3%

Verilog 1%

Stata 0.2%

Scilab 0.1%