add shl&shr
This commit is contained in:
@@ -60,5 +60,4 @@ set_global_assignment -name QIP_FILE ram0.qip
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@@ -20,9 +20,9 @@ refer to the applicable agreement for further details.
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*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 16 16 184 224)
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(rect 16 16 184 256)
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(text "alu" (rect 5 0 15 12)(font "Arial" ))
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(text "inst" (rect 8 192 20 204)(font "Arial" ))
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(text "inst" (rect 8 224 20 236)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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@@ -75,23 +75,37 @@ refer to the applicable agreement for further details.
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(port
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(pt 0 144)
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(input)
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(text "en_D" (rect 0 0 22 12)(font "Arial" ))
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(text "en_D" (rect 21 139 43 151)(font "Arial" ))
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(text "en_SHL" (rect 0 0 34 12)(font "Arial" ))
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(text "en_SHL" (rect 21 139 55 151)(font "Arial" ))
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(line (pt 0 144)(pt 16 144)(line_width 1))
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)
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(port
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(pt 0 160)
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(input)
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(text "accD[7..0]" (rect 0 0 41 12)(font "Arial" ))
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(text "accD[7..0]" (rect 21 155 62 167)(font "Arial" ))
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(line (pt 0 160)(pt 16 160)(line_width 3))
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(text "en_SHR" (rect 0 0 36 12)(font "Arial" ))
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(text "en_SHR" (rect 21 155 57 167)(font "Arial" ))
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(line (pt 0 160)(pt 16 160)(line_width 1))
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)
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(port
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(pt 0 176)
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(input)
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(text "en_D" (rect 0 0 22 12)(font "Arial" ))
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(text "en_D" (rect 21 171 43 183)(font "Arial" ))
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(line (pt 0 176)(pt 16 176)(line_width 1))
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)
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(port
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(pt 0 192)
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(input)
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(text "accD[7..0]" (rect 0 0 41 12)(font "Arial" ))
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(text "accD[7..0]" (rect 21 187 62 199)(font "Arial" ))
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(line (pt 0 192)(pt 16 192)(line_width 3))
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)
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(port
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(pt 0 208)
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(input)
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(text "dBus[7..0]" (rect 0 0 40 12)(font "Arial" ))
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(text "dBus[7..0]" (rect 21 171 61 183)(font "Arial" ))
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(line (pt 0 176)(pt 16 176)(line_width 3))
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(text "dBus[7..0]" (rect 21 203 61 215)(font "Arial" ))
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(line (pt 0 208)(pt 16 208)(line_width 3))
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)
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(port
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(pt 168 32)
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@@ -101,6 +115,6 @@ refer to the applicable agreement for further details.
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(line (pt 168 32)(pt 152 32)(line_width 3))
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)
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(drawing
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(rectangle (rect 16 16 152 192)(line_width 1))
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(rectangle (rect 16 16 152 224)(line_width 1))
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)
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)
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@@ -14,6 +14,8 @@ entity alu is
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en_Or: in std_logic;
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en_Not: in std_logic;
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en_NEG: in std_logic;
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en_SHL: in std_logic;
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en_SHR: in std_logic;
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en_D: in std_logic; -- 0时不运算 输出acc
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q:out std_logic_vector(7 downto 0); -- 输出
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accD:in std_logic_vector(7 downto 0); -- 输入
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@@ -40,6 +42,10 @@ signal regq: std_logic_vector(7 downto 0);
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regq<=not accD;
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elsif en_NEG='1' then
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regq<=(not accD) + 1;
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elsif en_SHL='1' then
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regq<= to_stdlogicvector(to_bitvector(accD) sll conv_integer(dbus));
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elsif en_SHR='1' then
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regq<= to_stdlogicvector(to_bitvector(accD) srl conv_integer(dbus));
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end if;
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end if;
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end if;
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@@ -6,9 +6,9 @@
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:01000500609A
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:010006008376
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:010007007088
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:010008009067
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:0100090000F6
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:01000A0000F5
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:010008008572
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:01000900A155
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:01000A00B243
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:01000B0000F4
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:01000C0000F3
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:01000D0000F2
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+33
-5
@@ -20,9 +20,9 @@ refer to the applicable agreement for further details.
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*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 16 16 256 416)
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(rect 16 16 256 448)
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(text "controller" (rect 5 0 40 12)(font "Arial" ))
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(text "inst" (rect 8 384 20 396)(font "Arial" ))
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(text "inst" (rect 8 416 20 428)(font "Arial" ))
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(port
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(pt 0 32)
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(input)
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@@ -152,9 +152,23 @@ refer to the applicable agreement for further details.
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(port
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(pt 0 320)
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(input)
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(text "i_SHL" (rect 0 0 25 12)(font "Arial" ))
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(text "i_SHL" (rect 21 315 46 327)(font "Arial" ))
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(line (pt 0 320)(pt 16 320)(line_width 1))
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)
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(port
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(pt 0 336)
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(input)
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(text "i_SHR" (rect 0 0 28 12)(font "Arial" ))
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(text "i_SHR" (rect 21 331 49 343)(font "Arial" ))
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(line (pt 0 336)(pt 16 336)(line_width 1))
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)
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(port
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(pt 0 352)
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(input)
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(text "data_num[3..0]" (rect 0 0 60 12)(font "Arial" ))
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(text "data_num[3..0]" (rect 21 315 81 327)(font "Arial" ))
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(line (pt 0 320)(pt 16 320)(line_width 3))
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(text "data_num[3..0]" (rect 21 347 81 359)(font "Arial" ))
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(line (pt 0 352)(pt 16 352)(line_width 3))
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)
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(port
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(pt 240 32)
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@@ -303,7 +317,21 @@ refer to the applicable agreement for further details.
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(text "o_NEG" (rect 188 347 219 359)(font "Arial" ))
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(line (pt 240 352)(pt 224 352)(line_width 1))
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)
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(port
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(pt 240 368)
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(output)
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(text "o_SHL" (rect 0 0 29 12)(font "Arial" ))
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(text "o_SHL" (rect 190 363 219 375)(font "Arial" ))
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(line (pt 240 368)(pt 224 368)(line_width 1))
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)
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(port
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(pt 240 384)
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(output)
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(text "o_SHR" (rect 0 0 31 12)(font "Arial" ))
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(text "o_SHR" (rect 188 379 219 391)(font "Arial" ))
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(line (pt 240 384)(pt 224 384)(line_width 1))
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)
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(drawing
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(rectangle (rect 16 16 224 384)(line_width 1))
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(rectangle (rect 16 16 224 416)(line_width 1))
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)
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)
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+25
-3
@@ -8,7 +8,7 @@ entity controller is
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port(
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clk: in std_logic;
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t0,t1,t2,t3,t4,t5,t6,t7: in std_logic; -- 节拍输入
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i_LOAD,i_STORE,i_ADD,i_SUB,i_AND,i_OR,i_NOT,i_NEG,i_HALT: in std_logic; -- 输入控制端
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i_LOAD,i_STORE,i_ADD,i_SUB,i_AND,i_OR,i_NOT,i_NEG,i_HALT,i_SHL,i_SHR: in std_logic; -- 输入控制端
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data_num: in std_logic_vector(3 downto 0);
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en_ALU_D: out std_logic; -- ACC使能
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en_PC: out std_logic; -- PC使能
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@@ -24,7 +24,7 @@ entity controller is
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data_out: out std_logic_vector(7 downto 0);
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clr_ACC:out std_logic;
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en_dBus,en_ALU: out std_logic;
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o_ADD,o_SUB,o_AND,o_OR,o_NOT,o_NEG: out std_logic
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o_ADD,o_SUB,o_AND,o_OR,o_NOT,o_NEG,o_SHL,o_SHR: out std_logic
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);
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end controller;
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@@ -95,6 +95,12 @@ begin
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elsif i_NEG='1' then
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en_ALU_D<='1';
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o_NEG<='1';
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elsif i_SHL='1' then
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en_ALU_D<='1';
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o_SHL<='1';
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elsif i_SHR='1' then
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en_ALU_D<='1';
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o_SHR<='1';
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end if;
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elsif t6='1' then
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if i_LOAD='1' then -- 关闭acc 节拍复位
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@@ -123,7 +129,15 @@ begin
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en_ALU<='1';
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elsif i_NEG='1' then
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en_ALU_D<='0';
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o_NEG<='1';
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o_NEG<='0';
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en_ALU<='1';
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elsif i_SHL='1' then
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en_ALU_D<='0';
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o_SHL<='0';
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en_ALU<='1';
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elsif i_SHR='1' then
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en_ALU_D<='0';
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o_SHR<='0';
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en_ALU<='1';
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end if;
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elsif t7='1' then
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@@ -151,6 +165,14 @@ begin
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en_ALU<='0';
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clr_ME<='1';
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en_PC<='1';
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elsif i_SHL='1' then
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en_ALU<='0';
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clr_ME<='1';
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en_PC<='1';
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elsif i_SHR='1' then
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en_ALU<='0';
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clr_ME<='1';
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en_PC<='1';
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end if;
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else
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null;
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@@ -0,0 +1,7 @@
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1531278970268 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1531278970284 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 11 11:16:10 2018 " "Processing started: Wed Jul 11 11:16:10 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1531278970284 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1531278970284 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off 8bit_model -c 8bit_model " "Command: quartus_asm --read_settings_files=off --write_settings_files=off 8bit_model -c 8bit_model" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1531278970284 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1531278970956 ""}
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{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1531278971409 ""}
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{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1531278971440 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4698 " "Peak virtual memory: 4698 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1531278971721 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 11 11:16:11 2018 " "Processing ended: Wed Jul 11 11:16:11 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1531278971721 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1531278971721 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1531278971721 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1531278971721 ""}
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<?xml version="1.0" ?>
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<LOG_ROOT>
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<PROJECT NAME="8bit_model">
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</PROJECT>
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</LOG_ROOT>
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@@ -0,0 +1,100 @@
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v1
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IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
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IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
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IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
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IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
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IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
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IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
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IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
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IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
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IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
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IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
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IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
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IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
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IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
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IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
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IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
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||||
IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
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IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
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||||
IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,PASS,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,0 such failures found.,,I/O,,
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||||
IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
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IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
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||||
IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
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||||
IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
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||||
IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
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||||
IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
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||||
IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
|
||||
IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
|
||||
IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
|
||||
IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os.,Critical,0 such failures found.,,I/O,,
|
||||
IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 5 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
|
||||
IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,,
|
||||
IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
|
||||
IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000046;IO_000047;IO_000033;IO_000034;IO_000042,
|
||||
IO_RULES_MATRIX,Total Pass,0;0;0;0;0;58;0;0;58;58;0;57;0;0;1;0;57;1;0;0;0;57;0;0;0;0;0;58;0;0,
|
||||
IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
|
||||
IO_RULES_MATRIX,Total Inapplicable,58;58;58;58;58;0;58;58;0;0;58;1;58;58;57;58;1;57;58;58;58;1;58;58;58;58;58;0;58;58,
|
||||
IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
|
||||
IO_RULES_MATRIX,test_res,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,acc_out[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,acc_out[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,acc_out[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,acc_out[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,acc_out[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,acc_out[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,acc_out[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,acc_out[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,accD[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,accD[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,accD[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,accD[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,accD[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,accD[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,accD[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,accD[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,alu_out[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,alu_out[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,alu_out[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,alu_out[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,alu_out[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,alu_out[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,alu_out[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,alu_out[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ar_out[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ar_out[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ar_out[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ar_out[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ar_out[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ar_out[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ar_out[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ar_out[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,dBus[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,dBus[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,dBus[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,dBus[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,dBus[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,dBus[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,dBus[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,dBus[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,pc_out[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,pc_out[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,pc_out[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,pc_out[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,pc_out[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,pc_out[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,pc_out[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,pc_out[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ram0_out[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ram0_out[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ram0_out[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ram0_out[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ram0_out[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ram0_out[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ram0_out[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,ram0_out[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_MATRIX,clk,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable,
|
||||
IO_RULES_SUMMARY,Total I/O Rules,30,
|
||||
IO_RULES_SUMMARY,Number of I/O Rules Passed,9,
|
||||
IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
|
||||
IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
|
||||
IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,21,
|
||||
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@@ -1,3 +1,3 @@
|
||||
Quartus_Version = Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
|
||||
Version_Index = 469919232
|
||||
Creation_Time = Wed Jul 11 00:51:06 2018
|
||||
Creation_Time = Wed Jul 11 10:34:17 2018
|
||||
|
||||
@@ -0,0 +1,6 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1531279012436 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1531279012451 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Copyright (C) 2018 Intel Corporation. All rights reserved. " "Copyright (C) 2018 Intel Corporation. All rights reserved." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1531279012451 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Your use of Intel Corporation's design tools, logic functions " "Your use of Intel Corporation's design tools, logic functions " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1531279012451 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "and other software and tools, and its AMPP partner logic " "and other software and tools, and its AMPP partner logic " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1531279012451 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "functions, and any output files from any of the foregoing " "functions, and any output files from any of the foregoing " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1531279012451 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "(including device programming or simulation files), and any " "(including device programming or simulation files), and any " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1531279012451 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "associated documentation or information are expressly subject " "associated documentation or information are expressly subject " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1531279012451 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "to the terms and conditions of the Intel Program License " "to the terms and conditions of the Intel Program License " { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1531279012451 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Subscription Agreement, the Intel Quartus Prime License Agreement, " "Subscription Agreement, the Intel Quartus Prime License Agreement," { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1531279012451 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the Intel FPGA IP License Agreement, or other applicable license " "the Intel FPGA IP License Agreement, or other applicable license" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1531279012451 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "agreement, including, without limitation, that your use is for " "agreement, including, without limitation, that your use is for" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1531279012451 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "the sole purpose of programming logic devices manufactured by " "the sole purpose of programming logic devices manufactured by" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1531279012451 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "Intel and sold by Intel or its authorized distributors. Please " "Intel and sold by Intel or its authorized distributors. Please" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1531279012451 ""} { "Info" "IQEXE_START_BANNER_LEGAL" "refer to the applicable agreement for further details. " "refer to the applicable agreement for further details." { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1531279012451 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 11 11:16:51 2018 " "Processing started: Wed Jul 11 11:16:51 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1531279012451 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1531279012451 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=C:/Users/Cai.MY/Desktop/8bit_model/simulation/qsim/ 8bit_model -c 8bit_model " "Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=C:/Users/Cai.MY/Desktop/8bit_model/simulation/qsim/ 8bit_model -c 8bit_model" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1531279012451 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1531279013264 ""}
|
||||
{ "Info" "IWSC_DONE_HDL_GENERATION" "8bit_model.vho C:/Users/Cai.MY/Desktop/8bit_model/simulation/qsim// simulation " "Generated file 8bit_model.vho in folder \"C:/Users/Cai.MY/Desktop/8bit_model/simulation/qsim//\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1531279013451 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4658 " "Peak virtual memory: 4658 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1531279013498 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 11 11:16:53 2018 " "Processing ended: Wed Jul 11 11:16:53 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1531279013498 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1531279013498 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1531279013498 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1531279013498 ""}
|
||||
@@ -0,0 +1,50 @@
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1531278960239 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1531278960239 ""}
|
||||
{ "Info" "IMPP_MPP_AUTO_ASSIGNED_DEVICE" "8bit_model EP4CE6E22C6 " "Automatically selected device EP4CE6E22C6 for design 8bit_model" { } { } 0 119004 "Automatically selected device %2!s! for design %1!s!" 0 0 "Fitter" 0 -1 1531278960442 ""}
|
||||
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1531278960505 ""}
|
||||
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Fitter" 0 -1 1531278960505 ""}
|
||||
{ "Warning" "WMPP_MPP_RAM_IS_ACTUALLY_ROM_TOP" "" "Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example." { { "Info" "IMPP_MPP_RAM_IS_ACTUALLY_ROM_SUB" "ram0:ram0\|altsyncram:altsyncram_component\|altsyncram_d3r3:auto_generated\|ram_block1a7 " "Atom \"ram0:ram0\|altsyncram:altsyncram_component\|altsyncram_d3r3:auto_generated\|ram_block1a7\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" { } { } 0 119043 "Atom \"%1!s!\" is instantiated as RAM, but it is actually implemented as ROM function because the write logic is always disabled" 0 0 "Design Software" 0 -1 1531278960583 "|eight_bit_model|ram0:ram0|altsyncram:altsyncram_component|altsyncram_d3r3:auto_generated|ram_block1a7"} } { } 0 18550 "Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example." 0 0 "Fitter" 0 -1 1531278960583 ""}
|
||||
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1531278960692 ""}
|
||||
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1531278960724 ""}
|
||||
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10E22C6 " "Device EP4CE10E22C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1531278961958 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15E22C6 " "Device EP4CE15E22C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1531278961958 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22E22C6 " "Device EP4CE22E22C6 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1531278961958 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1531278961958 ""}
|
||||
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "5 " "Fitter converted 5 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ 6 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "C:/Users/Cai.MY/Desktop/8bit_model/" { { 0 { 0 ""} 0 518 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1531278961973 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ 8 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/Cai.MY/Desktop/8bit_model/" { { 0 { 0 ""} 0 520 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1531278961973 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ 12 " "Pin ~ALTERA_DCLK~ is reserved at location 12" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/Cai.MY/Desktop/8bit_model/" { { 0 { 0 ""} 0 522 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1531278961973 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ 13 " "Pin ~ALTERA_DATA0~ is reserved at location 13" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "C:/Users/Cai.MY/Desktop/8bit_model/" { { 0 { 0 ""} 0 524 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1531278961973 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_nCEO~ 101 " "Pin ~ALTERA_nCEO~ is reserved at location 101" { } { { "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/intelfpga_lite/18.0/quartus/bin64/pin_planner.ppl" { ~ALTERA_nCEO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/Cai.MY/Desktop/8bit_model/" { { 0 { 0 ""} 0 526 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1531278961973 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1531278961973 ""}
|
||||
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1531278961973 ""}
|
||||
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1531278961973 ""}
|
||||
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "58 58 " "No exact pin location assignment(s) for 58 pins of 58 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1531278962286 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "8bit_model.sdc " "Synopsys Design Constraints File file not found: '8bit_model.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1531278962520 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1531278962520 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1531278962536 ""}
|
||||
{ "Info" "ISTA_NO_UNCERTAINTY_FOUND" "" "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." { } { } 0 332154 "The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers." 0 0 "Fitter" 0 -1 1531278962536 ""}
|
||||
{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1531278962536 ""}
|
||||
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk~input (placed in PIN 23 (CLK1, DIFFCLK_0n)) " "Automatically promoted node clk~input (placed in PIN 23 (CLK1, DIFFCLK_0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1531278962567 ""} } { { "eight_bit_model.bdf" "" { Schematic "C:/Users/Cai.MY/Desktop/8bit_model/eight_bit_model.bdf" { { 16 200 376 32 "clk" "" } } } } { "temporary_test_loc" "" { Generic "C:/Users/Cai.MY/Desktop/8bit_model/" { { 0 { 0 ""} 0 515 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1531278962567 ""}
|
||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1531278962817 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1531278962817 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1531278962817 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1531278962833 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1531278962833 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1531278962833 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1531278962833 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1531278962833 ""}
|
||||
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1531278962848 ""}
|
||||
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1531278962848 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1531278962848 ""}
|
||||
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "57 unused 2.5V 0 57 0 " "Number of I/O pins in group: 57 (unused VREF, 2.5V VCCIO, 0 input, 57 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "2.5 V. " "I/O standards used: 2.5 V." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Design Software" 0 -1 1531278962848 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Design Software" 0 -1 1531278962848 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1531278962848 ""}
|
||||
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 5 6 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 5 total pin(s) used -- 6 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1531278962848 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 0 8 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 8 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1531278962848 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 11 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 11 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1531278962848 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 14 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 14 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1531278962848 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 13 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 13 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1531278962848 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 9 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 9 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1531278962848 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 13 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 13 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1531278962848 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 12 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 12 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Design Software" 0 -1 1531278962848 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Design Software" 0 -1 1531278962848 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1531278962848 ""}
|
||||
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1531278962895 ""}
|
||||
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1531278962895 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1531278963614 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1531278963723 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1531278963754 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1531278965285 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Fitter placement operations ending: elapsed time is 00:00:02" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1531278965285 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1531278965582 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X23_Y12 X34_Y24 " "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X23_Y12 to location X34_Y24" { } { { "loc" "" { Generic "C:/Users/Cai.MY/Desktop/8bit_model/" { { 1 { 0 "Router estimated peak interconnect usage is 1% of the available device resources in the region that extends from location X23_Y12 to location X34_Y24"} { { 12 { 0 ""} 23 12 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1531278966113 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1531278966113 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1531278966878 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1531278966878 ""}
|
||||
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1531278966894 ""}
|
||||
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.23 " "Total time spent on timing analysis during the Fitter is 0.23 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1531278967035 ""}
|
||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1531278967050 ""}
|
||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1531278967253 ""}
|
||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1531278967253 ""}
|
||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1531278967425 ""}
|
||||
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1531278967878 ""}
|
||||
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Cai.MY/Desktop/8bit_model/output_files/8bit_model.fit.smsg " "Generated suppressed messages file C:/Users/Cai.MY/Desktop/8bit_model/output_files/8bit_model.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1531278968269 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5310 " "Peak virtual memory: 5310 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1531278968644 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 11 11:16:08 2018 " "Processing ended: Wed Jul 11 11:16:08 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1531278968644 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1531278968644 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:12 " "Total CPU time (on all processors): 00:00:12" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1531278968644 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1531278968644 ""}
|
||||
@@ -0,0 +1,952 @@
|
||||
|eight_bit_model
|
||||
test_res <= controller:inst6.test_RESULT
|
||||
clk => controller:inst6.clk
|
||||
clk => metronome:inst.clk
|
||||
clk => ir:inst1.clk
|
||||
clk => dr:dr.clk
|
||||
clk => ram0:ram0.clock
|
||||
clk => ar:ar.clk
|
||||
clk => pc:pc.clk
|
||||
clk => accumulator:inst5.clk
|
||||
clk => alu:inst3.clk
|
||||
acc_out[0] <= accumulator:inst5.q[0]
|
||||
acc_out[1] <= accumulator:inst5.q[1]
|
||||
acc_out[2] <= accumulator:inst5.q[2]
|
||||
acc_out[3] <= accumulator:inst5.q[3]
|
||||
acc_out[4] <= accumulator:inst5.q[4]
|
||||
acc_out[5] <= accumulator:inst5.q[5]
|
||||
acc_out[6] <= accumulator:inst5.q[6]
|
||||
acc_out[7] <= accumulator:inst5.q[7]
|
||||
accD[0] <= accumulator:inst5.q[0]
|
||||
accD[1] <= accumulator:inst5.q[1]
|
||||
accD[2] <= accumulator:inst5.q[2]
|
||||
accD[3] <= accumulator:inst5.q[3]
|
||||
accD[4] <= accumulator:inst5.q[4]
|
||||
accD[5] <= accumulator:inst5.q[5]
|
||||
accD[6] <= accumulator:inst5.q[6]
|
||||
accD[7] <= accumulator:inst5.q[7]
|
||||
alu_out[0] <= alu:inst3.q[0]
|
||||
alu_out[1] <= alu:inst3.q[1]
|
||||
alu_out[2] <= alu:inst3.q[2]
|
||||
alu_out[3] <= alu:inst3.q[3]
|
||||
alu_out[4] <= alu:inst3.q[4]
|
||||
alu_out[5] <= alu:inst3.q[5]
|
||||
alu_out[6] <= alu:inst3.q[6]
|
||||
alu_out[7] <= alu:inst3.q[7]
|
||||
ar_out[0] <= ar:ar.addr_out[0]
|
||||
ar_out[1] <= ar:ar.addr_out[1]
|
||||
ar_out[2] <= ar:ar.addr_out[2]
|
||||
ar_out[3] <= ar:ar.addr_out[3]
|
||||
ar_out[4] <= ar:ar.addr_out[4]
|
||||
ar_out[5] <= ar:ar.addr_out[5]
|
||||
ar_out[6] <= ar:ar.addr_out[6]
|
||||
ar_out[7] <= ar:ar.addr_out[7]
|
||||
dBus[0] <= controller:inst6.data_out[0]
|
||||
dBus[1] <= controller:inst6.data_out[1]
|
||||
dBus[2] <= controller:inst6.data_out[2]
|
||||
dBus[3] <= controller:inst6.data_out[3]
|
||||
dBus[4] <= controller:inst6.data_out[4]
|
||||
dBus[5] <= controller:inst6.data_out[5]
|
||||
dBus[6] <= controller:inst6.data_out[6]
|
||||
dBus[7] <= controller:inst6.data_out[7]
|
||||
pc_out[0] <= pc:pc.pc_out[0]
|
||||
pc_out[1] <= pc:pc.pc_out[1]
|
||||
pc_out[2] <= pc:pc.pc_out[2]
|
||||
pc_out[3] <= pc:pc.pc_out[3]
|
||||
pc_out[4] <= pc:pc.pc_out[4]
|
||||
pc_out[5] <= pc:pc.pc_out[5]
|
||||
pc_out[6] <= pc:pc.pc_out[6]
|
||||
pc_out[7] <= pc:pc.pc_out[7]
|
||||
ram0_out[0] <= ram0:ram0.q[0]
|
||||
ram0_out[1] <= ram0:ram0.q[1]
|
||||
ram0_out[2] <= ram0:ram0.q[2]
|
||||
ram0_out[3] <= ram0:ram0.q[3]
|
||||
ram0_out[4] <= ram0:ram0.q[4]
|
||||
ram0_out[5] <= ram0:ram0.q[5]
|
||||
ram0_out[6] <= ram0:ram0.q[6]
|
||||
ram0_out[7] <= ram0:ram0.q[7]
|
||||
|
||||
|
||||
|eight_bit_model|controller:inst6
|
||||
clk => test_RESULT~reg0.CLK
|
||||
clk => o_SHR~reg0.CLK
|
||||
clk => o_SHL~reg0.CLK
|
||||
clk => o_NEG~reg0.CLK
|
||||
clk => o_NOT~reg0.CLK
|
||||
clk => o_OR~reg0.CLK
|
||||
clk => o_AND~reg0.CLK
|
||||
clk => o_SUB~reg0.CLK
|
||||
clk => o_ADD~reg0.CLK
|
||||
clk => data_out[0]~reg0.CLK
|
||||
clk => data_out[1]~reg0.CLK
|
||||
clk => data_out[2]~reg0.CLK
|
||||
clk => data_out[3]~reg0.CLK
|
||||
clk => data_out[4]~reg0.CLK
|
||||
clk => data_out[5]~reg0.CLK
|
||||
clk => data_out[6]~reg0.CLK
|
||||
clk => data_out[7]~reg0.CLK
|
||||
clk => en_ALU~reg0.CLK
|
||||
clk => en_dBus~reg0.CLK
|
||||
clk => clr_ACC~reg0.CLK
|
||||
clk => clr_PC~reg0.CLK
|
||||
clk => clr_ME~reg0.CLK
|
||||
clk => w_RAM_data[0]~reg0.CLK
|
||||
clk => w_RAM_data[1]~reg0.CLK
|
||||
clk => w_RAM_data[2]~reg0.CLK
|
||||
clk => w_RAM_data[3]~reg0.CLK
|
||||
clk => w_RAM_data[4]~reg0.CLK
|
||||
clk => w_RAM_data[5]~reg0.CLK
|
||||
clk => w_RAM_data[6]~reg0.CLK
|
||||
clk => w_RAM_data[7]~reg0.CLK
|
||||
clk => w_RAM_addr[0]~reg0.CLK
|
||||
clk => w_RAM_addr[1]~reg0.CLK
|
||||
clk => w_RAM_addr[2]~reg0.CLK
|
||||
clk => w_RAM_addr[3]~reg0.CLK
|
||||
clk => w_RAM_addr[4]~reg0.CLK
|
||||
clk => w_RAM_addr[5]~reg0.CLK
|
||||
clk => w_RAM_addr[6]~reg0.CLK
|
||||
clk => w_RAM_addr[7]~reg0.CLK
|
||||
clk => w_RAM~reg0.CLK
|
||||
clk => en_IR~reg0.CLK
|
||||
clk => en_DR~reg0.CLK
|
||||
clk => en_AR~reg0.CLK
|
||||
clk => en_PC~reg0.CLK
|
||||
clk => en_ALU_D~reg0.CLK
|
||||
t0 => en_PC.OUTPUTSELECT
|
||||
t0 => en_ALU.OUTPUTSELECT
|
||||
t0 => en_dBus.OUTPUTSELECT
|
||||
t0 => clr_PC.OUTPUTSELECT
|
||||
t0 => clr_ME.OUTPUTSELECT
|
||||
t0 => en_ALU_D.OUTPUTSELECT
|
||||
t0 => o_ADD.OUTPUTSELECT
|
||||
t0 => o_SUB.OUTPUTSELECT
|
||||
t0 => o_AND.OUTPUTSELECT
|
||||
t0 => o_OR.OUTPUTSELECT
|
||||
t0 => o_NOT.OUTPUTSELECT
|
||||
t0 => o_NEG.OUTPUTSELECT
|
||||
t0 => o_SHR~reg0.ENA
|
||||
t0 => o_SHL~reg0.ENA
|
||||
t1 => en_PC.OUTPUTSELECT
|
||||
t1 => en_ALU.OUTPUTSELECT
|
||||
t1 => en_dBus.OUTPUTSELECT
|
||||
t1 => clr_PC.OUTPUTSELECT
|
||||
t1 => clr_ME.OUTPUTSELECT
|
||||
t1 => en_ALU_D.OUTPUTSELECT
|
||||
t1 => o_ADD.OUTPUTSELECT
|
||||
t1 => o_SUB.OUTPUTSELECT
|
||||
t1 => o_AND.OUTPUTSELECT
|
||||
t1 => o_OR.OUTPUTSELECT
|
||||
t1 => o_NOT.OUTPUTSELECT
|
||||
t1 => o_NEG.OUTPUTSELECT
|
||||
t1 => o_SHL.OUTPUTSELECT
|
||||
t1 => o_SHR.OUTPUTSELECT
|
||||
t2 => en_PC.OUTPUTSELECT
|
||||
t2 => en_ALU.OUTPUTSELECT
|
||||
t2 => en_dBus.OUTPUTSELECT
|
||||
t2 => clr_PC.OUTPUTSELECT
|
||||
t2 => clr_ME.OUTPUTSELECT
|
||||
t2 => en_ALU_D.OUTPUTSELECT
|
||||
t2 => o_ADD.OUTPUTSELECT
|
||||
t2 => o_SUB.OUTPUTSELECT
|
||||
t2 => o_AND.OUTPUTSELECT
|
||||
t2 => o_OR.OUTPUTSELECT
|
||||
t2 => o_NOT.OUTPUTSELECT
|
||||
t2 => o_NEG.OUTPUTSELECT
|
||||
t2 => o_SHL.OUTPUTSELECT
|
||||
t2 => o_SHR.OUTPUTSELECT
|
||||
t3 => en_PC.OUTPUTSELECT
|
||||
t3 => en_ALU.OUTPUTSELECT
|
||||
t3 => en_dBus.OUTPUTSELECT
|
||||
t3 => clr_PC.OUTPUTSELECT
|
||||
t3 => clr_ME.OUTPUTSELECT
|
||||
t3 => en_ALU_D.OUTPUTSELECT
|
||||
t3 => o_ADD.OUTPUTSELECT
|
||||
t3 => o_SUB.OUTPUTSELECT
|
||||
t3 => o_AND.OUTPUTSELECT
|
||||
t3 => o_OR.OUTPUTSELECT
|
||||
t3 => o_NOT.OUTPUTSELECT
|
||||
t3 => o_NEG.OUTPUTSELECT
|
||||
t3 => o_SHL.OUTPUTSELECT
|
||||
t3 => o_SHR.OUTPUTSELECT
|
||||
t4 => en_PC.OUTPUTSELECT
|
||||
t4 => en_ALU.OUTPUTSELECT
|
||||
t4 => en_dBus.OUTPUTSELECT
|
||||
t4 => clr_PC.OUTPUTSELECT
|
||||
t4 => clr_ME.OUTPUTSELECT
|
||||
t4 => en_ALU_D.OUTPUTSELECT
|
||||
t4 => o_ADD.OUTPUTSELECT
|
||||
t4 => o_SUB.OUTPUTSELECT
|
||||
t4 => o_AND.OUTPUTSELECT
|
||||
t4 => o_OR.OUTPUTSELECT
|
||||
t4 => o_NOT.OUTPUTSELECT
|
||||
t4 => o_NEG.OUTPUTSELECT
|
||||
t4 => o_SHL.OUTPUTSELECT
|
||||
t4 => o_SHR.OUTPUTSELECT
|
||||
t5 => en_PC.OUTPUTSELECT
|
||||
t5 => en_ALU.OUTPUTSELECT
|
||||
t5 => en_dBus.OUTPUTSELECT
|
||||
t5 => clr_PC.OUTPUTSELECT
|
||||
t5 => clr_ME.OUTPUTSELECT
|
||||
t5 => en_ALU_D.OUTPUTSELECT
|
||||
t5 => o_ADD.OUTPUTSELECT
|
||||
t5 => o_SUB.OUTPUTSELECT
|
||||
t5 => o_AND.OUTPUTSELECT
|
||||
t5 => o_OR.OUTPUTSELECT
|
||||
t5 => o_NOT.OUTPUTSELECT
|
||||
t5 => o_NEG.OUTPUTSELECT
|
||||
t5 => o_SHL.OUTPUTSELECT
|
||||
t5 => o_SHR.OUTPUTSELECT
|
||||
t6 => en_PC.OUTPUTSELECT
|
||||
t6 => en_ALU.OUTPUTSELECT
|
||||
t6 => o_SHL.OUTPUTSELECT
|
||||
t6 => o_SHR.OUTPUTSELECT
|
||||
t7 => en_PC.OUTPUTSELECT
|
||||
i_LOAD => clr_ME.OUTPUTSELECT
|
||||
i_LOAD => en_ALU_D.OUTPUTSELECT
|
||||
i_LOAD => o_ADD.OUTPUTSELECT
|
||||
i_LOAD => o_SUB.OUTPUTSELECT
|
||||
i_LOAD => o_AND.OUTPUTSELECT
|
||||
i_LOAD => o_OR.OUTPUTSELECT
|
||||
i_LOAD => o_NOT.OUTPUTSELECT
|
||||
i_LOAD => o_NEG.OUTPUTSELECT
|
||||
i_LOAD => o_SHL.OUTPUTSELECT
|
||||
i_LOAD => o_SHR.OUTPUTSELECT
|
||||
i_LOAD => en_ALU.OUTPUTSELECT
|
||||
i_LOAD => o_SHL.OUTPUTSELECT
|
||||
i_LOAD => o_SHR.OUTPUTSELECT
|
||||
i_LOAD => en_PC.DATAB
|
||||
i_LOAD => en_dBus.DATAB
|
||||
i_LOAD => test_RESULT~reg0.DATAIN
|
||||
i_STORE => ~NO_FANOUT~
|
||||
i_ADD => en_ALU_D.OUTPUTSELECT
|
||||
i_ADD => o_ADD.DATAA
|
||||
i_ADD => o_SUB.OUTPUTSELECT
|
||||
i_ADD => o_AND.OUTPUTSELECT
|
||||
i_ADD => o_OR.OUTPUTSELECT
|
||||
i_ADD => o_NOT.OUTPUTSELECT
|
||||
i_ADD => o_NEG.OUTPUTSELECT
|
||||
i_ADD => o_SHL.OUTPUTSELECT
|
||||
i_ADD => o_SHR.OUTPUTSELECT
|
||||
i_ADD => o_SHL.OUTPUTSELECT
|
||||
i_ADD => o_SHR.OUTPUTSELECT
|
||||
i_SUB => en_ALU_D.OUTPUTSELECT
|
||||
i_SUB => o_SUB.DATAA
|
||||
i_SUB => o_AND.OUTPUTSELECT
|
||||
i_SUB => o_OR.OUTPUTSELECT
|
||||
i_SUB => o_NOT.OUTPUTSELECT
|
||||
i_SUB => o_NEG.OUTPUTSELECT
|
||||
i_SUB => o_SHL.OUTPUTSELECT
|
||||
i_SUB => o_SHR.OUTPUTSELECT
|
||||
i_SUB => o_SHL.OUTPUTSELECT
|
||||
i_SUB => o_SHR.OUTPUTSELECT
|
||||
i_AND => en_ALU_D.OUTPUTSELECT
|
||||
i_AND => o_AND.DATAA
|
||||
i_AND => o_OR.OUTPUTSELECT
|
||||
i_AND => o_NOT.OUTPUTSELECT
|
||||
i_AND => o_NEG.OUTPUTSELECT
|
||||
i_AND => o_SHL.OUTPUTSELECT
|
||||
i_AND => o_SHR.OUTPUTSELECT
|
||||
i_AND => o_SHL.OUTPUTSELECT
|
||||
i_AND => o_SHR.OUTPUTSELECT
|
||||
i_OR => en_ALU_D.OUTPUTSELECT
|
||||
i_OR => o_OR.DATAA
|
||||
i_OR => o_NOT.OUTPUTSELECT
|
||||
i_OR => o_NEG.OUTPUTSELECT
|
||||
i_OR => o_SHL.OUTPUTSELECT
|
||||
i_OR => o_SHR.OUTPUTSELECT
|
||||
i_OR => o_SHL.OUTPUTSELECT
|
||||
i_OR => o_SHR.OUTPUTSELECT
|
||||
i_NOT => en_ALU_D.OUTPUTSELECT
|
||||
i_NOT => o_NOT.DATAA
|
||||
i_NOT => o_NEG.OUTPUTSELECT
|
||||
i_NOT => o_SHL.OUTPUTSELECT
|
||||
i_NOT => o_SHR.OUTPUTSELECT
|
||||
i_NOT => o_SHL.OUTPUTSELECT
|
||||
i_NOT => o_SHR.OUTPUTSELECT
|
||||
i_NEG => en_ALU_D.OUTPUTSELECT
|
||||
i_NEG => o_NEG.DATAA
|
||||
i_NEG => o_SHL.OUTPUTSELECT
|
||||
i_NEG => o_SHR.OUTPUTSELECT
|
||||
i_NEG => o_SHL.OUTPUTSELECT
|
||||
i_NEG => o_SHR.OUTPUTSELECT
|
||||
i_HALT => clr_ME.DATAA
|
||||
i_HALT => en_ALU_D.OUTPUTSELECT
|
||||
i_HALT => o_ADD.OUTPUTSELECT
|
||||
i_HALT => o_SUB.OUTPUTSELECT
|
||||
i_HALT => o_AND.OUTPUTSELECT
|
||||
i_HALT => o_OR.OUTPUTSELECT
|
||||
i_HALT => o_NOT.OUTPUTSELECT
|
||||
i_HALT => o_NEG.OUTPUTSELECT
|
||||
i_HALT => o_SHL.OUTPUTSELECT
|
||||
i_HALT => o_SHR.OUTPUTSELECT
|
||||
i_SHL => en_ALU_D.OUTPUTSELECT
|
||||
i_SHL => o_SHL.OUTPUTSELECT
|
||||
i_SHL => o_SHR.OUTPUTSELECT
|
||||
i_SHL => o_SHL.OUTPUTSELECT
|
||||
i_SHL => o_SHR.OUTPUTSELECT
|
||||
i_SHR => en_ALU_D.DATAA
|
||||
i_SHR => o_SHR.OUTPUTSELECT
|
||||
i_SHR => o_SHR.OUTPUTSELECT
|
||||
data_num[0] => data_out[0]~reg0.DATAIN
|
||||
data_num[1] => data_out[1]~reg0.DATAIN
|
||||
data_num[2] => data_out[2]~reg0.DATAIN
|
||||
data_num[3] => data_out[3]~reg0.DATAIN
|
||||
en_ALU_D <= en_ALU_D~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
en_PC <= en_PC~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
en_AR <= en_AR~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
en_DR <= en_DR~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
clr_ME <= clr_ME~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
en_IR <= en_IR~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
w_RAM <= w_RAM~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
w_RAM_data[0] <= w_RAM_data[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
w_RAM_data[1] <= w_RAM_data[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
w_RAM_data[2] <= w_RAM_data[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
w_RAM_data[3] <= w_RAM_data[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
w_RAM_data[4] <= w_RAM_data[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
w_RAM_data[5] <= w_RAM_data[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
w_RAM_data[6] <= w_RAM_data[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
w_RAM_data[7] <= w_RAM_data[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
w_RAM_addr[0] <= w_RAM_addr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
w_RAM_addr[1] <= w_RAM_addr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
w_RAM_addr[2] <= w_RAM_addr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
w_RAM_addr[3] <= w_RAM_addr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
w_RAM_addr[4] <= w_RAM_addr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
w_RAM_addr[5] <= w_RAM_addr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
w_RAM_addr[6] <= w_RAM_addr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
w_RAM_addr[7] <= w_RAM_addr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
test_RESULT <= test_RESULT~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
clr_PC <= clr_PC~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
data_out[0] <= data_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
data_out[1] <= data_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
data_out[2] <= data_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
data_out[3] <= data_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
data_out[4] <= data_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
data_out[5] <= data_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
data_out[6] <= data_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
data_out[7] <= data_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
clr_ACC <= clr_ACC~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
en_dBus <= en_dBus~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
en_ALU <= en_ALU~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
o_ADD <= o_ADD~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
o_SUB <= o_SUB~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
o_AND <= o_AND~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
o_OR <= o_OR~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
o_NOT <= o_NOT~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
o_NEG <= o_NEG~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
o_SHL <= o_SHL~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
o_SHR <= o_SHR~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|eight_bit_model|metronome:inst
|
||||
clk => tmp[0].CLK
|
||||
clk => tmp[1].CLK
|
||||
clk => tmp[2].CLK
|
||||
clk => tmp[3].CLK
|
||||
clk => tmp[4].CLK
|
||||
clk => tmp[5].CLK
|
||||
clk => tmp[6].CLK
|
||||
clk => tmp[7].CLK
|
||||
clr => tmp[0].PRESET
|
||||
clr => tmp[1].ACLR
|
||||
clr => tmp[2].ACLR
|
||||
clr => tmp[3].ACLR
|
||||
clr => tmp[4].ACLR
|
||||
clr => tmp[5].ACLR
|
||||
clr => tmp[6].ACLR
|
||||
clr => tmp[7].ACLR
|
||||
t0 <= tmp[0].DB_MAX_OUTPUT_PORT_TYPE
|
||||
t1 <= tmp[1].DB_MAX_OUTPUT_PORT_TYPE
|
||||
t2 <= tmp[2].DB_MAX_OUTPUT_PORT_TYPE
|
||||
t3 <= tmp[3].DB_MAX_OUTPUT_PORT_TYPE
|
||||
t4 <= tmp[4].DB_MAX_OUTPUT_PORT_TYPE
|
||||
t5 <= tmp[5].DB_MAX_OUTPUT_PORT_TYPE
|
||||
t6 <= tmp[6].DB_MAX_OUTPUT_PORT_TYPE
|
||||
t7 <= tmp[7].DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|eight_bit_model|ir:inst1
|
||||
clk => regq[0].CLK
|
||||
clk => regq[1].CLK
|
||||
clk => regq[2].CLK
|
||||
clk => regq[3].CLK
|
||||
clk => regq[4].CLK
|
||||
clk => regq[5].CLK
|
||||
clk => regq[6].CLK
|
||||
clk => regq[7].CLK
|
||||
en_D => regq[0].ENA
|
||||
en_D => regq[1].ENA
|
||||
en_D => regq[2].ENA
|
||||
en_D => regq[3].ENA
|
||||
en_D => regq[4].ENA
|
||||
en_D => regq[5].ENA
|
||||
en_D => regq[6].ENA
|
||||
en_D => regq[7].ENA
|
||||
DATA_IN[0] => regq[0].DATAIN
|
||||
DATA_IN[1] => regq[1].DATAIN
|
||||
DATA_IN[2] => regq[2].DATAIN
|
||||
DATA_IN[3] => regq[3].DATAIN
|
||||
DATA_IN[4] => regq[4].DATAIN
|
||||
DATA_IN[5] => regq[5].DATAIN
|
||||
DATA_IN[6] => regq[6].DATAIN
|
||||
DATA_IN[7] => regq[7].DATAIN
|
||||
o_LOAD <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
|
||||
o_STORE <= Mux0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
o_ADD <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
|
||||
o_SUB <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
|
||||
o_AND <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
|
||||
o_OR <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
|
||||
o_NOT <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
|
||||
o_NEG <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
|
||||
o_HALT <= Mux8.DB_MAX_OUTPUT_PORT_TYPE
|
||||
o_SHL <= Mux9.DB_MAX_OUTPUT_PORT_TYPE
|
||||
o_SHR <= Mux10.DB_MAX_OUTPUT_PORT_TYPE
|
||||
DATA_OUT[0] <= regq[0].DB_MAX_OUTPUT_PORT_TYPE
|
||||
DATA_OUT[1] <= regq[1].DB_MAX_OUTPUT_PORT_TYPE
|
||||
DATA_OUT[2] <= regq[2].DB_MAX_OUTPUT_PORT_TYPE
|
||||
DATA_OUT[3] <= regq[3].DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|eight_bit_model|dr:dr
|
||||
clk => regq[0].CLK
|
||||
clk => regq[1].CLK
|
||||
clk => regq[2].CLK
|
||||
clk => regq[3].CLK
|
||||
clk => regq[4].CLK
|
||||
clk => regq[5].CLK
|
||||
clk => regq[6].CLK
|
||||
clk => regq[7].CLK
|
||||
en_D => regq[0].ENA
|
||||
en_D => regq[1].ENA
|
||||
en_D => regq[2].ENA
|
||||
en_D => regq[3].ENA
|
||||
en_D => regq[4].ENA
|
||||
en_D => regq[5].ENA
|
||||
en_D => regq[6].ENA
|
||||
en_D => regq[7].ENA
|
||||
data_in[0] => regq[0].DATAIN
|
||||
data_in[1] => regq[1].DATAIN
|
||||
data_in[2] => regq[2].DATAIN
|
||||
data_in[3] => regq[3].DATAIN
|
||||
data_in[4] => regq[4].DATAIN
|
||||
data_in[5] => regq[5].DATAIN
|
||||
data_in[6] => regq[6].DATAIN
|
||||
data_in[7] => regq[7].DATAIN
|
||||
data_out[0] <= regq[0].DB_MAX_OUTPUT_PORT_TYPE
|
||||
data_out[1] <= regq[1].DB_MAX_OUTPUT_PORT_TYPE
|
||||
data_out[2] <= regq[2].DB_MAX_OUTPUT_PORT_TYPE
|
||||
data_out[3] <= regq[3].DB_MAX_OUTPUT_PORT_TYPE
|
||||
data_out[4] <= regq[4].DB_MAX_OUTPUT_PORT_TYPE
|
||||
data_out[5] <= regq[5].DB_MAX_OUTPUT_PORT_TYPE
|
||||
data_out[6] <= regq[6].DB_MAX_OUTPUT_PORT_TYPE
|
||||
data_out[7] <= regq[7].DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|eight_bit_model|ram0:ram0
|
||||
address[0] => altsyncram:altsyncram_component.address_a[0]
|
||||
address[1] => altsyncram:altsyncram_component.address_a[1]
|
||||
address[2] => altsyncram:altsyncram_component.address_a[2]
|
||||
address[3] => altsyncram:altsyncram_component.address_a[3]
|
||||
address[4] => altsyncram:altsyncram_component.address_a[4]
|
||||
address[5] => altsyncram:altsyncram_component.address_a[5]
|
||||
address[6] => altsyncram:altsyncram_component.address_a[6]
|
||||
address[7] => altsyncram:altsyncram_component.address_a[7]
|
||||
clock => altsyncram:altsyncram_component.clock0
|
||||
data[0] => altsyncram:altsyncram_component.data_a[0]
|
||||
data[1] => altsyncram:altsyncram_component.data_a[1]
|
||||
data[2] => altsyncram:altsyncram_component.data_a[2]
|
||||
data[3] => altsyncram:altsyncram_component.data_a[3]
|
||||
data[4] => altsyncram:altsyncram_component.data_a[4]
|
||||
data[5] => altsyncram:altsyncram_component.data_a[5]
|
||||
data[6] => altsyncram:altsyncram_component.data_a[6]
|
||||
data[7] => altsyncram:altsyncram_component.data_a[7]
|
||||
wren => altsyncram:altsyncram_component.wren_a
|
||||
q[0] <= altsyncram:altsyncram_component.q_a[0]
|
||||
q[1] <= altsyncram:altsyncram_component.q_a[1]
|
||||
q[2] <= altsyncram:altsyncram_component.q_a[2]
|
||||
q[3] <= altsyncram:altsyncram_component.q_a[3]
|
||||
q[4] <= altsyncram:altsyncram_component.q_a[4]
|
||||
q[5] <= altsyncram:altsyncram_component.q_a[5]
|
||||
q[6] <= altsyncram:altsyncram_component.q_a[6]
|
||||
q[7] <= altsyncram:altsyncram_component.q_a[7]
|
||||
|
||||
|
||||
|eight_bit_model|ram0:ram0|altsyncram:altsyncram_component
|
||||
wren_a => altsyncram_d3r3:auto_generated.wren_a
|
||||
rden_a => ~NO_FANOUT~
|
||||
wren_b => ~NO_FANOUT~
|
||||
rden_b => ~NO_FANOUT~
|
||||
data_a[0] => altsyncram_d3r3:auto_generated.data_a[0]
|
||||
data_a[1] => altsyncram_d3r3:auto_generated.data_a[1]
|
||||
data_a[2] => altsyncram_d3r3:auto_generated.data_a[2]
|
||||
data_a[3] => altsyncram_d3r3:auto_generated.data_a[3]
|
||||
data_a[4] => altsyncram_d3r3:auto_generated.data_a[4]
|
||||
data_a[5] => altsyncram_d3r3:auto_generated.data_a[5]
|
||||
data_a[6] => altsyncram_d3r3:auto_generated.data_a[6]
|
||||
data_a[7] => altsyncram_d3r3:auto_generated.data_a[7]
|
||||
data_b[0] => ~NO_FANOUT~
|
||||
address_a[0] => altsyncram_d3r3:auto_generated.address_a[0]
|
||||
address_a[1] => altsyncram_d3r3:auto_generated.address_a[1]
|
||||
address_a[2] => altsyncram_d3r3:auto_generated.address_a[2]
|
||||
address_a[3] => altsyncram_d3r3:auto_generated.address_a[3]
|
||||
address_a[4] => altsyncram_d3r3:auto_generated.address_a[4]
|
||||
address_a[5] => altsyncram_d3r3:auto_generated.address_a[5]
|
||||
address_a[6] => altsyncram_d3r3:auto_generated.address_a[6]
|
||||
address_a[7] => altsyncram_d3r3:auto_generated.address_a[7]
|
||||
address_b[0] => ~NO_FANOUT~
|
||||
addressstall_a => ~NO_FANOUT~
|
||||
addressstall_b => ~NO_FANOUT~
|
||||
clock0 => altsyncram_d3r3:auto_generated.clock0
|
||||
clock1 => ~NO_FANOUT~
|
||||
clocken0 => ~NO_FANOUT~
|
||||
clocken1 => ~NO_FANOUT~
|
||||
clocken2 => ~NO_FANOUT~
|
||||
clocken3 => ~NO_FANOUT~
|
||||
aclr0 => ~NO_FANOUT~
|
||||
aclr1 => ~NO_FANOUT~
|
||||
byteena_a[0] => ~NO_FANOUT~
|
||||
byteena_b[0] => ~NO_FANOUT~
|
||||
q_a[0] <= altsyncram_d3r3:auto_generated.q_a[0]
|
||||
q_a[1] <= altsyncram_d3r3:auto_generated.q_a[1]
|
||||
q_a[2] <= altsyncram_d3r3:auto_generated.q_a[2]
|
||||
q_a[3] <= altsyncram_d3r3:auto_generated.q_a[3]
|
||||
q_a[4] <= altsyncram_d3r3:auto_generated.q_a[4]
|
||||
q_a[5] <= altsyncram_d3r3:auto_generated.q_a[5]
|
||||
q_a[6] <= altsyncram_d3r3:auto_generated.q_a[6]
|
||||
q_a[7] <= altsyncram_d3r3:auto_generated.q_a[7]
|
||||
q_b[0] <= <GND>
|
||||
eccstatus[0] <= <GND>
|
||||
eccstatus[1] <= <GND>
|
||||
eccstatus[2] <= <GND>
|
||||
|
||||
|
||||
|eight_bit_model|ram0:ram0|altsyncram:altsyncram_component|altsyncram_d3r3:auto_generated
|
||||
address_a[0] => ram_block1a0.PORTAADDR
|
||||
address_a[0] => ram_block1a1.PORTAADDR
|
||||
address_a[0] => ram_block1a2.PORTAADDR
|
||||
address_a[0] => ram_block1a3.PORTAADDR
|
||||
address_a[0] => ram_block1a4.PORTAADDR
|
||||
address_a[0] => ram_block1a5.PORTAADDR
|
||||
address_a[0] => ram_block1a6.PORTAADDR
|
||||
address_a[0] => ram_block1a7.PORTAADDR
|
||||
address_a[1] => ram_block1a0.PORTAADDR1
|
||||
address_a[1] => ram_block1a1.PORTAADDR1
|
||||
address_a[1] => ram_block1a2.PORTAADDR1
|
||||
address_a[1] => ram_block1a3.PORTAADDR1
|
||||
address_a[1] => ram_block1a4.PORTAADDR1
|
||||
address_a[1] => ram_block1a5.PORTAADDR1
|
||||
address_a[1] => ram_block1a6.PORTAADDR1
|
||||
address_a[1] => ram_block1a7.PORTAADDR1
|
||||
address_a[2] => ram_block1a0.PORTAADDR2
|
||||
address_a[2] => ram_block1a1.PORTAADDR2
|
||||
address_a[2] => ram_block1a2.PORTAADDR2
|
||||
address_a[2] => ram_block1a3.PORTAADDR2
|
||||
address_a[2] => ram_block1a4.PORTAADDR2
|
||||
address_a[2] => ram_block1a5.PORTAADDR2
|
||||
address_a[2] => ram_block1a6.PORTAADDR2
|
||||
address_a[2] => ram_block1a7.PORTAADDR2
|
||||
address_a[3] => ram_block1a0.PORTAADDR3
|
||||
address_a[3] => ram_block1a1.PORTAADDR3
|
||||
address_a[3] => ram_block1a2.PORTAADDR3
|
||||
address_a[3] => ram_block1a3.PORTAADDR3
|
||||
address_a[3] => ram_block1a4.PORTAADDR3
|
||||
address_a[3] => ram_block1a5.PORTAADDR3
|
||||
address_a[3] => ram_block1a6.PORTAADDR3
|
||||
address_a[3] => ram_block1a7.PORTAADDR3
|
||||
address_a[4] => ram_block1a0.PORTAADDR4
|
||||
address_a[4] => ram_block1a1.PORTAADDR4
|
||||
address_a[4] => ram_block1a2.PORTAADDR4
|
||||
address_a[4] => ram_block1a3.PORTAADDR4
|
||||
address_a[4] => ram_block1a4.PORTAADDR4
|
||||
address_a[4] => ram_block1a5.PORTAADDR4
|
||||
address_a[4] => ram_block1a6.PORTAADDR4
|
||||
address_a[4] => ram_block1a7.PORTAADDR4
|
||||
address_a[5] => ram_block1a0.PORTAADDR5
|
||||
address_a[5] => ram_block1a1.PORTAADDR5
|
||||
address_a[5] => ram_block1a2.PORTAADDR5
|
||||
address_a[5] => ram_block1a3.PORTAADDR5
|
||||
address_a[5] => ram_block1a4.PORTAADDR5
|
||||
address_a[5] => ram_block1a5.PORTAADDR5
|
||||
address_a[5] => ram_block1a6.PORTAADDR5
|
||||
address_a[5] => ram_block1a7.PORTAADDR5
|
||||
address_a[6] => ram_block1a0.PORTAADDR6
|
||||
address_a[6] => ram_block1a1.PORTAADDR6
|
||||
address_a[6] => ram_block1a2.PORTAADDR6
|
||||
address_a[6] => ram_block1a3.PORTAADDR6
|
||||
address_a[6] => ram_block1a4.PORTAADDR6
|
||||
address_a[6] => ram_block1a5.PORTAADDR6
|
||||
address_a[6] => ram_block1a6.PORTAADDR6
|
||||
address_a[6] => ram_block1a7.PORTAADDR6
|
||||
address_a[7] => ram_block1a0.PORTAADDR7
|
||||
address_a[7] => ram_block1a1.PORTAADDR7
|
||||
address_a[7] => ram_block1a2.PORTAADDR7
|
||||
address_a[7] => ram_block1a3.PORTAADDR7
|
||||
address_a[7] => ram_block1a4.PORTAADDR7
|
||||
address_a[7] => ram_block1a5.PORTAADDR7
|
||||
address_a[7] => ram_block1a6.PORTAADDR7
|
||||
address_a[7] => ram_block1a7.PORTAADDR7
|
||||
clock0 => ram_block1a0.CLK0
|
||||
clock0 => ram_block1a1.CLK0
|
||||
clock0 => ram_block1a2.CLK0
|
||||
clock0 => ram_block1a3.CLK0
|
||||
clock0 => ram_block1a4.CLK0
|
||||
clock0 => ram_block1a5.CLK0
|
||||
clock0 => ram_block1a6.CLK0
|
||||
clock0 => ram_block1a7.CLK0
|
||||
data_a[0] => ram_block1a0.PORTADATAIN
|
||||
data_a[1] => ram_block1a1.PORTADATAIN
|
||||
data_a[2] => ram_block1a2.PORTADATAIN
|
||||
data_a[3] => ram_block1a3.PORTADATAIN
|
||||
data_a[4] => ram_block1a4.PORTADATAIN
|
||||
data_a[5] => ram_block1a5.PORTADATAIN
|
||||
data_a[6] => ram_block1a6.PORTADATAIN
|
||||
data_a[7] => ram_block1a7.PORTADATAIN
|
||||
q_a[0] <= ram_block1a0.PORTADATAOUT
|
||||
q_a[1] <= ram_block1a1.PORTADATAOUT
|
||||
q_a[2] <= ram_block1a2.PORTADATAOUT
|
||||
q_a[3] <= ram_block1a3.PORTADATAOUT
|
||||
q_a[4] <= ram_block1a4.PORTADATAOUT
|
||||
q_a[5] <= ram_block1a5.PORTADATAOUT
|
||||
q_a[6] <= ram_block1a6.PORTADATAOUT
|
||||
q_a[7] <= ram_block1a7.PORTADATAOUT
|
||||
wren_a => ram_block1a0.PORTAWE
|
||||
wren_a => ram_block1a1.PORTAWE
|
||||
wren_a => ram_block1a2.PORTAWE
|
||||
wren_a => ram_block1a3.PORTAWE
|
||||
wren_a => ram_block1a4.PORTAWE
|
||||
wren_a => ram_block1a5.PORTAWE
|
||||
wren_a => ram_block1a6.PORTAWE
|
||||
wren_a => ram_block1a7.PORTAWE
|
||||
|
||||
|
||||
|eight_bit_model|ar:ar
|
||||
clk => addr_out[0]~reg0.CLK
|
||||
clk => addr_out[1]~reg0.CLK
|
||||
clk => addr_out[2]~reg0.CLK
|
||||
clk => addr_out[3]~reg0.CLK
|
||||
clk => addr_out[4]~reg0.CLK
|
||||
clk => addr_out[5]~reg0.CLK
|
||||
clk => addr_out[6]~reg0.CLK
|
||||
clk => addr_out[7]~reg0.CLK
|
||||
en_D => addr_out[0]~reg0.ENA
|
||||
en_D => addr_out[1]~reg0.ENA
|
||||
en_D => addr_out[2]~reg0.ENA
|
||||
en_D => addr_out[3]~reg0.ENA
|
||||
en_D => addr_out[4]~reg0.ENA
|
||||
en_D => addr_out[5]~reg0.ENA
|
||||
en_D => addr_out[6]~reg0.ENA
|
||||
en_D => addr_out[7]~reg0.ENA
|
||||
addr_in[0] => addr_out[0]~reg0.DATAIN
|
||||
addr_in[1] => addr_out[1]~reg0.DATAIN
|
||||
addr_in[2] => addr_out[2]~reg0.DATAIN
|
||||
addr_in[3] => addr_out[3]~reg0.DATAIN
|
||||
addr_in[4] => addr_out[4]~reg0.DATAIN
|
||||
addr_in[5] => addr_out[5]~reg0.DATAIN
|
||||
addr_in[6] => addr_out[6]~reg0.DATAIN
|
||||
addr_in[7] => addr_out[7]~reg0.DATAIN
|
||||
addr_out[0] <= addr_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
addr_out[1] <= addr_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
addr_out[2] <= addr_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
addr_out[3] <= addr_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
addr_out[4] <= addr_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
addr_out[5] <= addr_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
addr_out[6] <= addr_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
addr_out[7] <= addr_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|eight_bit_model|pc:pc
|
||||
clk => pcout[0].CLK
|
||||
clk => pcout[1].CLK
|
||||
clk => pcout[2].CLK
|
||||
clk => pcout[3].CLK
|
||||
clk => pcout[4].CLK
|
||||
clk => pcout[5].CLK
|
||||
clk => pcout[6].CLK
|
||||
clk => pcout[7].CLK
|
||||
clr => pcout[0].ACLR
|
||||
clr => pcout[1].ACLR
|
||||
clr => pcout[2].ACLR
|
||||
clr => pcout[3].ACLR
|
||||
clr => pcout[4].ACLR
|
||||
clr => pcout[5].ACLR
|
||||
clr => pcout[6].ACLR
|
||||
clr => pcout[7].ACLR
|
||||
en_D => pcout[7].ENA
|
||||
en_D => pcout[6].ENA
|
||||
en_D => pcout[5].ENA
|
||||
en_D => pcout[4].ENA
|
||||
en_D => pcout[3].ENA
|
||||
en_D => pcout[2].ENA
|
||||
en_D => pcout[1].ENA
|
||||
en_D => pcout[0].ENA
|
||||
pc_out[0] <= pcout[0].DB_MAX_OUTPUT_PORT_TYPE
|
||||
pc_out[1] <= pcout[1].DB_MAX_OUTPUT_PORT_TYPE
|
||||
pc_out[2] <= pcout[2].DB_MAX_OUTPUT_PORT_TYPE
|
||||
pc_out[3] <= pcout[3].DB_MAX_OUTPUT_PORT_TYPE
|
||||
pc_out[4] <= pcout[4].DB_MAX_OUTPUT_PORT_TYPE
|
||||
pc_out[5] <= pcout[5].DB_MAX_OUTPUT_PORT_TYPE
|
||||
pc_out[6] <= pcout[6].DB_MAX_OUTPUT_PORT_TYPE
|
||||
pc_out[7] <= pcout[7].DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|eight_bit_model|accumulator:inst5
|
||||
clk => accReg[0].CLK
|
||||
clk => accReg[1].CLK
|
||||
clk => accReg[2].CLK
|
||||
clk => accReg[3].CLK
|
||||
clk => accReg[4].CLK
|
||||
clk => accReg[5].CLK
|
||||
clk => accReg[6].CLK
|
||||
clk => accReg[7].CLK
|
||||
reset => accReg.OUTPUTSELECT
|
||||
reset => accReg.OUTPUTSELECT
|
||||
reset => accReg.OUTPUTSELECT
|
||||
reset => accReg.OUTPUTSELECT
|
||||
reset => accReg.OUTPUTSELECT
|
||||
reset => accReg.OUTPUTSELECT
|
||||
reset => accReg.OUTPUTSELECT
|
||||
reset => accReg.OUTPUTSELECT
|
||||
en_dBus => accReg.OUTPUTSELECT
|
||||
en_dBus => accReg.OUTPUTSELECT
|
||||
en_dBus => accReg.OUTPUTSELECT
|
||||
en_dBus => accReg.OUTPUTSELECT
|
||||
en_dBus => accReg.OUTPUTSELECT
|
||||
en_dBus => accReg.OUTPUTSELECT
|
||||
en_dBus => accReg.OUTPUTSELECT
|
||||
en_dBus => accReg.OUTPUTSELECT
|
||||
en_Alu => accReg.OUTPUTSELECT
|
||||
en_Alu => accReg.OUTPUTSELECT
|
||||
en_Alu => accReg.OUTPUTSELECT
|
||||
en_Alu => accReg.OUTPUTSELECT
|
||||
en_Alu => accReg.OUTPUTSELECT
|
||||
en_Alu => accReg.OUTPUTSELECT
|
||||
en_Alu => accReg.OUTPUTSELECT
|
||||
en_Alu => accReg.OUTPUTSELECT
|
||||
aluD[0] => accReg.DATAB
|
||||
aluD[1] => accReg.DATAB
|
||||
aluD[2] => accReg.DATAB
|
||||
aluD[3] => accReg.DATAB
|
||||
aluD[4] => accReg.DATAB
|
||||
aluD[5] => accReg.DATAB
|
||||
aluD[6] => accReg.DATAB
|
||||
aluD[7] => accReg.DATAB
|
||||
dBus[0] => accReg.DATAB
|
||||
dBus[1] => accReg.DATAB
|
||||
dBus[2] => accReg.DATAB
|
||||
dBus[3] => accReg.DATAB
|
||||
dBus[4] => accReg.DATAB
|
||||
dBus[5] => accReg.DATAB
|
||||
dBus[6] => accReg.DATAB
|
||||
dBus[7] => accReg.DATAB
|
||||
q[0] <= accReg[0].DB_MAX_OUTPUT_PORT_TYPE
|
||||
q[1] <= accReg[1].DB_MAX_OUTPUT_PORT_TYPE
|
||||
q[2] <= accReg[2].DB_MAX_OUTPUT_PORT_TYPE
|
||||
q[3] <= accReg[3].DB_MAX_OUTPUT_PORT_TYPE
|
||||
q[4] <= accReg[4].DB_MAX_OUTPUT_PORT_TYPE
|
||||
q[5] <= accReg[5].DB_MAX_OUTPUT_PORT_TYPE
|
||||
q[6] <= accReg[6].DB_MAX_OUTPUT_PORT_TYPE
|
||||
q[7] <= accReg[7].DB_MAX_OUTPUT_PORT_TYPE
|
||||
|
||||
|
||||
|eight_bit_model|alu:inst3
|
||||
clk => regq[0].CLK
|
||||
clk => regq[1].CLK
|
||||
clk => regq[2].CLK
|
||||
clk => regq[3].CLK
|
||||
clk => regq[4].CLK
|
||||
clk => regq[5].CLK
|
||||
clk => regq[6].CLK
|
||||
clk => regq[7].CLK
|
||||
en_Add => regq.OUTPUTSELECT
|
||||
en_Add => regq.OUTPUTSELECT
|
||||
en_Add => regq.OUTPUTSELECT
|
||||
en_Add => regq.OUTPUTSELECT
|
||||
en_Add => regq.OUTPUTSELECT
|
||||
en_Add => regq.OUTPUTSELECT
|
||||
en_Add => regq.OUTPUTSELECT
|
||||
en_Add => regq.OUTPUTSELECT
|
||||
en_Sub => regq.OUTPUTSELECT
|
||||
en_Sub => regq.OUTPUTSELECT
|
||||
en_Sub => regq.OUTPUTSELECT
|
||||
en_Sub => regq.OUTPUTSELECT
|
||||
en_Sub => regq.OUTPUTSELECT
|
||||
en_Sub => regq.OUTPUTSELECT
|
||||
en_Sub => regq.OUTPUTSELECT
|
||||
en_Sub => regq.OUTPUTSELECT
|
||||
en_And => regq.OUTPUTSELECT
|
||||
en_And => regq.OUTPUTSELECT
|
||||
en_And => regq.OUTPUTSELECT
|
||||
en_And => regq.OUTPUTSELECT
|
||||
en_And => regq.OUTPUTSELECT
|
||||
en_And => regq.OUTPUTSELECT
|
||||
en_And => regq.OUTPUTSELECT
|
||||
en_And => regq.OUTPUTSELECT
|
||||
en_Or => regq.OUTPUTSELECT
|
||||
en_Or => regq.OUTPUTSELECT
|
||||
en_Or => regq.OUTPUTSELECT
|
||||
en_Or => regq.OUTPUTSELECT
|
||||
en_Or => regq.OUTPUTSELECT
|
||||
en_Or => regq.OUTPUTSELECT
|
||||
en_Or => regq.OUTPUTSELECT
|
||||
en_Or => regq.OUTPUTSELECT
|
||||
en_Not => regq.OUTPUTSELECT
|
||||
en_Not => regq.OUTPUTSELECT
|
||||
en_Not => regq.OUTPUTSELECT
|
||||
en_Not => regq.OUTPUTSELECT
|
||||
en_Not => regq.OUTPUTSELECT
|
||||
en_Not => regq.OUTPUTSELECT
|
||||
en_Not => regq.OUTPUTSELECT
|
||||
en_Not => regq.OUTPUTSELECT
|
||||
en_NEG => regq.OUTPUTSELECT
|
||||
en_NEG => regq.OUTPUTSELECT
|
||||
en_NEG => regq.OUTPUTSELECT
|
||||
en_NEG => regq.OUTPUTSELECT
|
||||
en_NEG => regq.OUTPUTSELECT
|
||||
en_NEG => regq.OUTPUTSELECT
|
||||
en_NEG => regq.OUTPUTSELECT
|
||||
en_NEG => regq.OUTPUTSELECT
|
||||
en_SHL => regq.OUTPUTSELECT
|
||||
en_SHL => regq.OUTPUTSELECT
|
||||
en_SHL => regq.OUTPUTSELECT
|
||||
en_SHL => regq.OUTPUTSELECT
|
||||
en_SHL => regq.OUTPUTSELECT
|
||||
en_SHL => regq.OUTPUTSELECT
|
||||
en_SHL => regq.OUTPUTSELECT
|
||||
en_SHL => regq.OUTPUTSELECT
|
||||
en_SHR => regq.OUTPUTSELECT
|
||||
en_SHR => regq.OUTPUTSELECT
|
||||
en_SHR => regq.OUTPUTSELECT
|
||||
en_SHR => regq.OUTPUTSELECT
|
||||
en_SHR => regq.OUTPUTSELECT
|
||||
en_SHR => regq.OUTPUTSELECT
|
||||
en_SHR => regq.OUTPUTSELECT
|
||||
en_SHR => regq.OUTPUTSELECT
|
||||
en_D => regq[0].ENA
|
||||
en_D => regq[1].ENA
|
||||
en_D => regq[2].ENA
|
||||
en_D => regq[3].ENA
|
||||
en_D => regq[4].ENA
|
||||
en_D => regq[5].ENA
|
||||
en_D => regq[6].ENA
|
||||
en_D => regq[7].ENA
|
||||
q[0] <= regq[0].DB_MAX_OUTPUT_PORT_TYPE
|
||||
q[1] <= regq[1].DB_MAX_OUTPUT_PORT_TYPE
|
||||
q[2] <= regq[2].DB_MAX_OUTPUT_PORT_TYPE
|
||||
q[3] <= regq[3].DB_MAX_OUTPUT_PORT_TYPE
|
||||
q[4] <= regq[4].DB_MAX_OUTPUT_PORT_TYPE
|
||||
q[5] <= regq[5].DB_MAX_OUTPUT_PORT_TYPE
|
||||
q[6] <= regq[6].DB_MAX_OUTPUT_PORT_TYPE
|
||||
q[7] <= regq[7].DB_MAX_OUTPUT_PORT_TYPE
|
||||
accD[0] => Add0.IN8
|
||||
accD[0] => Add1.IN16
|
||||
accD[0] => regq.IN0
|
||||
accD[0] => regq.IN0
|
||||
accD[0] => ShiftLeft0.IN8
|
||||
accD[0] => ShiftRight0.IN8
|
||||
accD[0] => Add2.IN16
|
||||
accD[0] => regq.DATAB
|
||||
accD[1] => Add0.IN7
|
||||
accD[1] => Add1.IN15
|
||||
accD[1] => regq.IN0
|
||||
accD[1] => regq.IN0
|
||||
accD[1] => ShiftLeft0.IN7
|
||||
accD[1] => ShiftRight0.IN7
|
||||
accD[1] => Add2.IN15
|
||||
accD[1] => regq.DATAB
|
||||
accD[2] => Add0.IN6
|
||||
accD[2] => Add1.IN14
|
||||
accD[2] => regq.IN0
|
||||
accD[2] => regq.IN0
|
||||
accD[2] => ShiftLeft0.IN6
|
||||
accD[2] => ShiftRight0.IN6
|
||||
accD[2] => Add2.IN14
|
||||
accD[2] => regq.DATAB
|
||||
accD[3] => Add0.IN5
|
||||
accD[3] => Add1.IN13
|
||||
accD[3] => regq.IN0
|
||||
accD[3] => regq.IN0
|
||||
accD[3] => ShiftLeft0.IN5
|
||||
accD[3] => ShiftRight0.IN5
|
||||
accD[3] => Add2.IN13
|
||||
accD[3] => regq.DATAB
|
||||
accD[4] => Add0.IN4
|
||||
accD[4] => Add1.IN12
|
||||
accD[4] => regq.IN0
|
||||
accD[4] => regq.IN0
|
||||
accD[4] => ShiftLeft0.IN4
|
||||
accD[4] => ShiftRight0.IN4
|
||||
accD[4] => Add2.IN12
|
||||
accD[4] => regq.DATAB
|
||||
accD[5] => Add0.IN3
|
||||
accD[5] => Add1.IN11
|
||||
accD[5] => regq.IN0
|
||||
accD[5] => regq.IN0
|
||||
accD[5] => ShiftLeft0.IN3
|
||||
accD[5] => ShiftRight0.IN3
|
||||
accD[5] => Add2.IN11
|
||||
accD[5] => regq.DATAB
|
||||
accD[6] => Add0.IN2
|
||||
accD[6] => Add1.IN10
|
||||
accD[6] => regq.IN0
|
||||
accD[6] => regq.IN0
|
||||
accD[6] => ShiftLeft0.IN2
|
||||
accD[6] => ShiftRight0.IN2
|
||||
accD[6] => Add2.IN10
|
||||
accD[6] => regq.DATAB
|
||||
accD[7] => Add0.IN1
|
||||
accD[7] => Add1.IN9
|
||||
accD[7] => regq.IN0
|
||||
accD[7] => regq.IN0
|
||||
accD[7] => ShiftLeft0.IN1
|
||||
accD[7] => ShiftRight0.IN1
|
||||
accD[7] => Add2.IN9
|
||||
accD[7] => regq.DATAB
|
||||
dBus[0] => Add0.IN16
|
||||
dBus[0] => regq.IN1
|
||||
dBus[0] => regq.IN1
|
||||
dBus[0] => ShiftLeft0.IN16
|
||||
dBus[0] => ShiftRight0.IN16
|
||||
dBus[0] => Add1.IN8
|
||||
dBus[1] => Add0.IN15
|
||||
dBus[1] => regq.IN1
|
||||
dBus[1] => regq.IN1
|
||||
dBus[1] => ShiftLeft0.IN15
|
||||
dBus[1] => ShiftRight0.IN15
|
||||
dBus[1] => Add1.IN7
|
||||
dBus[2] => Add0.IN14
|
||||
dBus[2] => regq.IN1
|
||||
dBus[2] => regq.IN1
|
||||
dBus[2] => ShiftLeft0.IN14
|
||||
dBus[2] => ShiftRight0.IN14
|
||||
dBus[2] => Add1.IN6
|
||||
dBus[3] => Add0.IN13
|
||||
dBus[3] => regq.IN1
|
||||
dBus[3] => regq.IN1
|
||||
dBus[3] => ShiftLeft0.IN13
|
||||
dBus[3] => ShiftRight0.IN13
|
||||
dBus[3] => Add1.IN5
|
||||
dBus[4] => Add0.IN12
|
||||
dBus[4] => regq.IN1
|
||||
dBus[4] => regq.IN1
|
||||
dBus[4] => ShiftLeft0.IN12
|
||||
dBus[4] => ShiftRight0.IN12
|
||||
dBus[4] => Add1.IN4
|
||||
dBus[5] => Add0.IN11
|
||||
dBus[5] => regq.IN1
|
||||
dBus[5] => regq.IN1
|
||||
dBus[5] => ShiftLeft0.IN11
|
||||
dBus[5] => ShiftRight0.IN11
|
||||
dBus[5] => Add1.IN3
|
||||
dBus[6] => Add0.IN10
|
||||
dBus[6] => regq.IN1
|
||||
dBus[6] => regq.IN1
|
||||
dBus[6] => ShiftLeft0.IN10
|
||||
dBus[6] => ShiftRight0.IN10
|
||||
dBus[6] => Add1.IN2
|
||||
dBus[7] => Add0.IN9
|
||||
dBus[7] => regq.IN1
|
||||
dBus[7] => regq.IN1
|
||||
dBus[7] => ShiftLeft0.IN9
|
||||
dBus[7] => ShiftRight0.IN9
|
||||
dBus[7] => Add1.IN1
|
||||
|
||||
|
||||
Binary file not shown.
@@ -0,0 +1,178 @@
|
||||
<TABLE>
|
||||
<TR bgcolor="#C0C0C0">
|
||||
<TH>Hierarchy</TH>
|
||||
<TH>Input</TH>
|
||||
<TH>Constant Input</TH>
|
||||
<TH>Unused Input</TH>
|
||||
<TH>Floating Input</TH>
|
||||
<TH>Output</TH>
|
||||
<TH>Constant Output</TH>
|
||||
<TH>Unused Output</TH>
|
||||
<TH>Floating Output</TH>
|
||||
<TH>Bidir</TH>
|
||||
<TH>Constant Bidir</TH>
|
||||
<TH>Unused Bidir</TH>
|
||||
<TH>Input only Bidir</TH>
|
||||
<TH>Output only Bidir</TH>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >inst3</TD>
|
||||
<TD >26</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >8</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >inst5</TD>
|
||||
<TD >20</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >8</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >pc</TD>
|
||||
<TD >3</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >8</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >ar</TD>
|
||||
<TD >10</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >8</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >ram0|altsyncram_component|auto_generated</TD>
|
||||
<TD >18</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >8</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >ram0</TD>
|
||||
<TD >9</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >8</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >dr</TD>
|
||||
<TD >10</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >8</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >inst1</TD>
|
||||
<TD >10</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >15</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >inst</TD>
|
||||
<TD >2</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >8</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
<TR >
|
||||
<TD >inst6</TD>
|
||||
<TD >24</TD>
|
||||
<TD >17</TD>
|
||||
<TD >1</TD>
|
||||
<TD >17</TD>
|
||||
<TD >44</TD>
|
||||
<TD >17</TD>
|
||||
<TD >17</TD>
|
||||
<TD >17</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
<TD >0</TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
Binary file not shown.
@@ -0,0 +1,16 @@
|
||||
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
; Legal Partition Candidates ;
|
||||
+------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
|
||||
+------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
; inst3 ; 26 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; inst5 ; 20 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; pc ; 3 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; ar ; 10 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; ram0|altsyncram_component|auto_generated ; 18 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; ram0 ; 9 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; dr ; 10 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; inst1 ; 10 ; 0 ; 0 ; 0 ; 15 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; inst ; 2 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
; inst6 ; 24 ; 17 ; 1 ; 17 ; 44 ; 17 ; 17 ; 17 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
||||
+------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
|
||||
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|
||||
v1
|
||||
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|
||||
v1
|
||||
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|
||||
SOURCE
|
||||
@@ -0,0 +1,42 @@
|
||||
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1531278973814 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition " "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1531278973830 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 11 11:16:13 2018 " "Processing started: Wed Jul 11 11:16:13 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1531278973830 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1531278973830 ""}
|
||||
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta 8bit_model -c 8bit_model " "Command: quartus_sta 8bit_model -c 8bit_model" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1531278973830 ""}
|
||||
{ "Info" "0" "" "qsta_default_script.tcl version: #2" { } { } 0 0 "qsta_default_script.tcl version: #2" 0 0 "Timing Analyzer" 0 0 1531278974361 ""}
|
||||
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1531278975595 ""}
|
||||
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1531278975595 ""}
|
||||
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "High junction temperature 85 " "High junction temperature operating condition is not set. Assuming a default value of '85'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Timing Analyzer" 0 -1 1531278975673 ""}
|
||||
{ "Info" "ICUT_CUT_DEFAULT_OPERATING_CONDITION" "Low junction temperature 0 " "Low junction temperature operating condition is not set. Assuming a default value of '0'." { } { } 0 21076 "%1!s! operating condition is not set. Assuming a default value of '%2!s!'." 0 0 "Timing Analyzer" 0 -1 1531278975673 ""}
|
||||
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "8bit_model.sdc " "Synopsys Design Constraints File file not found: '8bit_model.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1531278975892 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Timing Analyzer" 0 -1 1531278975892 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1531278975892 ""} } { } 0 332105 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1531278975892 ""}
|
||||
{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Timing Analyzer" 0 -1 1531278975892 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1531278975892 ""}
|
||||
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1531278975892 ""}
|
||||
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1531278975908 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1531278975923 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1531278975923 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.467 " "Worst-case setup slack is -2.467" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278975923 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278975923 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.467 -79.592 clk " " -2.467 -79.592 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278975923 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1531278975923 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.308 " "Worst-case hold slack is 0.308" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278975923 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278975923 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.308 0.000 clk " " 0.308 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278975923 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1531278975923 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -0.278 " "Worst-case recovery slack is -0.278" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278975939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278975939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.278 -3.336 clk " " -0.278 -3.336 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278975939 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1531278975939 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.499 " "Worst-case removal slack is 0.499" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278975939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278975939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.499 0.000 clk " " 0.499 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278975939 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1531278975939 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278975939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278975939 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -99.740 clk " " -3.000 -99.740 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278975939 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1531278975939 ""}
|
||||
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1531278975986 ""}
|
||||
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1531278976017 ""}
|
||||
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1531278976439 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1531278976486 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1531278976501 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1531278976501 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -2.110 " "Worst-case setup slack is -2.110" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976501 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976501 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.110 -65.100 clk " " -2.110 -65.100 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976501 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1531278976501 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.262 " "Worst-case hold slack is 0.262" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976501 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976501 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.262 0.000 clk " " 0.262 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976501 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1531278976501 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery -0.148 " "Worst-case recovery slack is -0.148" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976501 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976501 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -0.148 -1.768 clk " " -0.148 -1.768 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976501 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1531278976501 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.433 " "Worst-case removal slack is 0.433" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976517 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976517 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.433 0.000 clk " " 0.433 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976517 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1531278976517 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976517 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976517 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -99.740 clk " " -3.000 -99.740 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976517 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1531278976517 ""}
|
||||
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1531278976564 ""}
|
||||
{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1531278976673 ""}
|
||||
{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer." 0 0 "Design Software" 0 -1 1531278976673 ""} } { } 1 332148 "Timing requirements not met" 0 0 "Timing Analyzer" 0 -1 1531278976673 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.001 " "Worst-case setup slack is -1.001" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.001 -19.997 clk " " -1.001 -19.997 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976673 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1531278976673 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.166 " "Worst-case hold slack is 0.166" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976673 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.166 0.000 clk " " 0.166 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976673 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1531278976673 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 0.275 " "Worst-case recovery slack is 0.275" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976689 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976689 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.275 0.000 clk " " 0.275 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976689 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1531278976689 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.283 " "Worst-case removal slack is 0.283" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976689 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976689 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.283 0.000 clk " " 0.283 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976689 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1531278976689 ""}
|
||||
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -3.000 " "Worst-case minimum pulse width slack is -3.000" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976704 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976704 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -3.000 -94.353 clk " " -3.000 -94.353 clk " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1531278976704 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1531278976704 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1531278977313 ""}
|
||||
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1531278977313 ""}
|
||||
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 5 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4775 " "Peak virtual memory: 4775 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1531278977392 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 11 11:16:17 2018 " "Processing ended: Wed Jul 11 11:16:17 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1531278977392 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1531278977392 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1531278977392 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1531278977392 ""}
|
||||
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@@ -0,0 +1,7 @@
|
||||
start_full_compilation:s:00:00:48
|
||||
start_analysis_synthesis:s:00:00:24-start_full_compilation
|
||||
start_analysis_elaboration:s-start_full_compilation
|
||||
start_fitter:s:00:00:11-start_full_compilation
|
||||
start_assembler:s:00:00:03-start_full_compilation
|
||||
start_timing_analyzer:s:00:00:06-start_full_compilation
|
||||
start_eda_netlist_writer:s:00:00:04-start_full_compilation
|
||||
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+159
-159
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+436
-349
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Load Diff
@@ -0,0 +1,11 @@
|
||||
This folder contains data for incremental compilation.
|
||||
|
||||
The compiled_partitions sub-folder contains previous compilation results for each partition.
|
||||
As long as this folder is preserved, incremental compilation results from earlier compiles
|
||||
can be re-used. To perform a clean compilation from source files for all partitions, both
|
||||
the db and incremental_db folder should be removed.
|
||||
|
||||
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
|
||||
As long as this folder is preserved, imported partitions will be automatically re-imported
|
||||
when the db or incremental_db/compiled_partitions folders are removed.
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user