c-my/8bit_model
1
0 Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
5 Commits 1 Branch 0 Tags
master
T
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
c-my e496002a07 finial
2018-07-24 11:22:17 +08:00
.qsys_edit
initial commit
2018-07-11 00:51:22 +08:00
db
finial
2018-07-24 11:22:17 +08:00
greybox_tmp
finial
2018-07-24 11:22:17 +08:00
incremental_db
finial
2018-07-24 11:22:17 +08:00
output_files
finial
2018-07-24 11:22:17 +08:00
simulation
finial
2018-07-24 11:22:17 +08:00
8bit_model_nativelink_simulation.rpt
initial commit
2018-07-11 00:51:22 +08:00
8bit_model.qpf
initial commit
2018-07-11 00:51:22 +08:00
8bit_model.qsf
finial
2018-07-24 11:22:17 +08:00
8bit_model.qws
finial
2018-07-24 11:22:17 +08:00
accumulator.bsf
initial commit
2018-07-11 00:51:22 +08:00
accumulator.vhd
initial commit
2018-07-11 00:51:22 +08:00
accumulator.vhd.bak
initial commit
2018-07-11 00:51:22 +08:00
alu.bsf
add shl&shr
2018-07-11 11:18:16 +08:00
alu.vhd
add shl&shr
2018-07-11 11:18:16 +08:00
alu.vhd.bak
initial commit
2018-07-11 00:51:22 +08:00
alu.vwf
initial commit
2018-07-11 00:51:22 +08:00
ar.bsf
initial commit
2018-07-11 00:51:22 +08:00
ar.vhd
initial commit
2018-07-11 00:51:22 +08:00
ar.vhd.bak
initial commit
2018-07-11 00:51:22 +08:00
ax301_ax4010.tcl
final
2018-07-12 00:14:47 +08:00
ax301_ax4010.tcl.bak
final
2018-07-12 00:14:47 +08:00
code.hex
finial
2018-07-24 11:22:17 +08:00
controller.bsf
finial
2018-07-24 11:22:17 +08:00
controller.vhd
finial
2018-07-24 11:22:17 +08:00
controller.vhd.bak
initial commit
2018-07-11 00:51:22 +08:00
dr.bsf
initial commit
2018-07-11 00:51:22 +08:00
dr.vhd
initial commit
2018-07-11 00:51:22 +08:00
dr.vhd.bak
initial commit
2018-07-11 00:51:22 +08:00
eight_bit_model.bdf
finial
2018-07-24 11:22:17 +08:00
ir.bsf
add shl&shr
2018-07-11 11:18:16 +08:00
ir.vhd
add shl&shr
2018-07-11 11:18:16 +08:00
ir.vhd.bak
initial commit
2018-07-11 00:51:22 +08:00
led.bsf
final
2018-07-12 00:14:47 +08:00
led.vhd
final
2018-07-12 00:14:47 +08:00
led.vhd.bak
final
2018-07-12 00:14:47 +08:00
metronome.bsf
initial commit
2018-07-11 00:51:22 +08:00
metronome.vhd
initial commit
2018-07-11 00:51:22 +08:00
metronome.vhd.bak
initial commit
2018-07-11 00:51:22 +08:00
pc.bsf
initial commit
2018-07-11 00:51:22 +08:00
pc.vhd
initial commit
2018-07-11 00:51:22 +08:00
pc.vhd.bak
initial commit
2018-07-11 00:51:22 +08:00
pll.bsf
final
2018-07-12 00:14:47 +08:00
pll.cmp
final
2018-07-12 00:14:47 +08:00
pll.ppf
final
2018-07-12 00:14:47 +08:00
pll.qip
final
2018-07-12 00:14:47 +08:00
pll.vhd
final
2018-07-12 00:14:47 +08:00
ram0_inst.vhd
initial commit
2018-07-11 00:51:22 +08:00
ram0.bsf
initial commit
2018-07-11 00:51:22 +08:00
ram0.cmp
initial commit
2018-07-11 00:51:22 +08:00
ram0.qip
initial commit
2018-07-11 00:51:22 +08:00
ram0.vhd
initial commit
2018-07-11 00:51:22 +08:00
Waveform1.vwf
finial
2018-07-24 11:22:17 +08:00
Waveform2.vwf
finial
2018-07-24 11:22:17 +08:00
Waveform3.vwf
finial
2018-07-24 11:22:17 +08:00
Waveform4.vwf
finial
2018-07-24 11:22:17 +08:00
Waveform5.vwf
finial
2018-07-24 11:22:17 +08:00
Waveform6.vwf
finial
2018-07-24 11:22:17 +08:00
Waveform7.vwf
finial
2018-07-24 11:22:17 +08:00
Waveform8.vwf
finial
2018-07-24 11:22:17 +08:00
Waveform.vwf
finial
2018-07-24 11:22:17 +08:00
指令表.xlsx
final
2018-07-12 00:14:47 +08:00
S
Description
数电课设 8位模型机
11 MiB
0 Stars 1 Watchers 0 Forks
Languages
VHDL 97.1%
Csound Document 1.3%
Verilog 1%
Stata 0.2%
Scilab 0.1%