31 lines
515 B
VHDL
31 lines
515 B
VHDL
-- 程序计数器
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-- 仿真通过
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity pc is
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port(
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clk,clr: in std_logic;
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en_D: in std_logic;
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pc_out: out std_logic_vector(7 downto 0)
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);
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end pc;
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architecture behav of pc is
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signal pcout:std_logic_vector(7 downto 0);
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begin
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process(clk,clr)
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begin
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if clr='1' then
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pcout<="00000000";
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elsif clk'event and clk='1' then
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if en_D='1' then
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pcout<=pcout+1;
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end if;
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end if;
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end process;
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pc_out<=pcout;
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end behav; |