36 lines
760 B
VHDL
36 lines
760 B
VHDL
-- 累加器
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library ieee;
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use ieee.std_logic_1164.all;
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entity accumulator is
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port(
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clk:in std_logic;
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reset: in std_logic;
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en_dBus:in std_logic; --dbus输入
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en_Alu:in std_logic; -- ALU输入
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aluD: in std_logic_vector(7 downto 0); -- 接ALU数据线
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dBus: in std_logic_vector(7 downto 0); -- 接数据总线
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q: out std_logic_vector(7 downto 0) -- 输出
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);
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end accumulator;
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architecture accArch of accumulator is
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signal accReg:std_logic_vector(7 downto 0);
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begin
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process(clk)
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begin
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if clk'event and clk='1' then
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if reset='1' then
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accReg<="00000000";
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elsif en_Alu='1' then
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accReg<=aluD; -- ALU输入
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elsif en_dBus='1' then
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accReg<=dbus; -- 总线输入
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end if;
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end if;
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end process;
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q<=accReg;
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end accArch; |