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c-my e496002a07 finial
2018-07-24 11:22:17 +08:00
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rtl_work
initial commit
2018-07-11 00:51:22 +08:00
8bit_model_6_1200mv_0c_slow.vho
final
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8bit_model_6_1200mv_0c_vhd_slow.sdo
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8bit_model_6_1200mv_85c_slow.vho
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8bit_model_6_1200mv_85c_vhd_slow.sdo
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8bit_model_8_1200mv_0c_slow.vho
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8bit_model_8_1200mv_0c_vhd_slow.sdo
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8bit_model_8_1200mv_85c_slow.vho
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2018-07-24 11:22:17 +08:00
8bit_model_8_1200mv_85c_vhd_slow.sdo
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8bit_model_min_1200mv_0c_fast.vho
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8bit_model_min_1200mv_0c_vhd_fast.sdo
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8bit_model_modelsim.xrf
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8bit_model_run_msim_rtl_vhdl.do
initial commit
2018-07-11 00:51:22 +08:00
8bit_model_vhd.sdo
finial
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8bit_model.sft
final
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8bit_model.vho
finial
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content.hex
initial commit
2018-07-11 00:51:22 +08:00
modelsim.ini
initial commit
2018-07-11 00:51:22 +08:00
msim_transcript
initial commit
2018-07-11 00:51:22 +08:00