597 lines
16 KiB
VHDL
597 lines
16 KiB
VHDL
-- Copyright (C) 2018 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details.
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-- VENDOR "Altera"
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-- PROGRAM "Quartus Prime"
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-- VERSION "Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition"
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-- DATE "07/13/2018 20:16:13"
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--
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-- Device: Altera EP4CE6F17C8 Package FBGA256
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--
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--
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-- This VHDL file should be used for ModelSim-Altera (VHDL) only
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--
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LIBRARY CYCLONEIVE;
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LIBRARY IEEE;
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USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
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USE IEEE.STD_LOGIC_1164.ALL;
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ENTITY hard_block IS
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PORT (
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devoe : IN std_logic;
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devclrn : IN std_logic;
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devpor : IN std_logic
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);
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END hard_block;
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-- Design Ports Information
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-- ~ALTERA_ASDO_DATA1~ => Location: PIN_C1, I/O Standard: 2.5 V, Current Strength: Default
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-- ~ALTERA_FLASH_nCE_nCSO~ => Location: PIN_D2, I/O Standard: 2.5 V, Current Strength: Default
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-- ~ALTERA_DCLK~ => Location: PIN_H1, I/O Standard: 2.5 V, Current Strength: Default
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-- ~ALTERA_DATA0~ => Location: PIN_H2, I/O Standard: 2.5 V, Current Strength: Default
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-- ~ALTERA_nCEO~ => Location: PIN_F16, I/O Standard: 2.5 V, Current Strength: 8mA
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ARCHITECTURE structure OF hard_block IS
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SIGNAL gnd : std_logic := '0';
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SIGNAL vcc : std_logic := '1';
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SIGNAL unknown : std_logic := 'X';
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SIGNAL ww_devoe : std_logic;
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SIGNAL ww_devclrn : std_logic;
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SIGNAL ww_devpor : std_logic;
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SIGNAL \~ALTERA_ASDO_DATA1~~padout\ : std_logic;
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SIGNAL \~ALTERA_FLASH_nCE_nCSO~~padout\ : std_logic;
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SIGNAL \~ALTERA_DATA0~~padout\ : std_logic;
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SIGNAL \~ALTERA_ASDO_DATA1~~ibuf_o\ : std_logic;
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SIGNAL \~ALTERA_FLASH_nCE_nCSO~~ibuf_o\ : std_logic;
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SIGNAL \~ALTERA_DATA0~~ibuf_o\ : std_logic;
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BEGIN
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ww_devoe <= devoe;
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ww_devclrn <= devclrn;
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ww_devpor <= devpor;
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END structure;
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LIBRARY ALTERA;
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LIBRARY CYCLONEIVE;
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LIBRARY IEEE;
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USE ALTERA.ALTERA_PRIMITIVES_COMPONENTS.ALL;
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USE CYCLONEIVE.CYCLONEIVE_COMPONENTS.ALL;
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USE IEEE.STD_LOGIC_1164.ALL;
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ENTITY ar IS
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PORT (
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clk : IN std_logic;
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en_D : IN std_logic;
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addr_in : IN std_logic_vector(7 DOWNTO 0);
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addr_out : BUFFER std_logic_vector(7 DOWNTO 0)
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);
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END ar;
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-- Design Ports Information
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-- addr_out[0] => Location: PIN_L2, I/O Standard: 2.5 V, Current Strength: Default
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-- addr_out[1] => Location: PIN_N9, I/O Standard: 2.5 V, Current Strength: Default
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-- addr_out[2] => Location: PIN_P6, I/O Standard: 2.5 V, Current Strength: Default
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-- addr_out[3] => Location: PIN_J2, I/O Standard: 2.5 V, Current Strength: Default
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-- addr_out[4] => Location: PIN_K5, I/O Standard: 2.5 V, Current Strength: Default
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-- addr_out[5] => Location: PIN_N6, I/O Standard: 2.5 V, Current Strength: Default
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-- addr_out[6] => Location: PIN_L1, I/O Standard: 2.5 V, Current Strength: Default
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-- addr_out[7] => Location: PIN_N5, I/O Standard: 2.5 V, Current Strength: Default
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-- addr_in[0] => Location: PIN_L3, I/O Standard: 2.5 V, Current Strength: Default
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-- clk => Location: PIN_E1, I/O Standard: 2.5 V, Current Strength: Default
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-- en_D => Location: PIN_L6, I/O Standard: 2.5 V, Current Strength: Default
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-- addr_in[1] => Location: PIN_N1, I/O Standard: 2.5 V, Current Strength: Default
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-- addr_in[2] => Location: PIN_T5, I/O Standard: 2.5 V, Current Strength: Default
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-- addr_in[3] => Location: PIN_T2, I/O Standard: 2.5 V, Current Strength: Default
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-- addr_in[4] => Location: PIN_N2, I/O Standard: 2.5 V, Current Strength: Default
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-- addr_in[5] => Location: PIN_B5, I/O Standard: 2.5 V, Current Strength: Default
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-- addr_in[6] => Location: PIN_K6, I/O Standard: 2.5 V, Current Strength: Default
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-- addr_in[7] => Location: PIN_R5, I/O Standard: 2.5 V, Current Strength: Default
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ARCHITECTURE structure OF ar IS
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SIGNAL gnd : std_logic := '0';
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SIGNAL vcc : std_logic := '1';
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SIGNAL unknown : std_logic := 'X';
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SIGNAL devoe : std_logic := '1';
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SIGNAL devclrn : std_logic := '1';
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SIGNAL devpor : std_logic := '1';
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SIGNAL ww_devoe : std_logic;
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SIGNAL ww_devclrn : std_logic;
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SIGNAL ww_devpor : std_logic;
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SIGNAL ww_clk : std_logic;
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SIGNAL ww_en_D : std_logic;
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SIGNAL ww_addr_in : std_logic_vector(7 DOWNTO 0);
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SIGNAL ww_addr_out : std_logic_vector(7 DOWNTO 0);
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SIGNAL \clk~inputclkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0);
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SIGNAL \addr_out[0]~output_o\ : std_logic;
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SIGNAL \addr_out[1]~output_o\ : std_logic;
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SIGNAL \addr_out[2]~output_o\ : std_logic;
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SIGNAL \addr_out[3]~output_o\ : std_logic;
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SIGNAL \addr_out[4]~output_o\ : std_logic;
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SIGNAL \addr_out[5]~output_o\ : std_logic;
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SIGNAL \addr_out[6]~output_o\ : std_logic;
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SIGNAL \addr_out[7]~output_o\ : std_logic;
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SIGNAL \clk~input_o\ : std_logic;
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SIGNAL \clk~inputclkctrl_outclk\ : std_logic;
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SIGNAL \addr_in[0]~input_o\ : std_logic;
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SIGNAL \addr_out[0]~reg0feeder_combout\ : std_logic;
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SIGNAL \en_D~input_o\ : std_logic;
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SIGNAL \addr_out[0]~reg0_q\ : std_logic;
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SIGNAL \addr_in[1]~input_o\ : std_logic;
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SIGNAL \addr_out[1]~reg0_q\ : std_logic;
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SIGNAL \addr_in[2]~input_o\ : std_logic;
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SIGNAL \addr_out[2]~reg0feeder_combout\ : std_logic;
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SIGNAL \addr_out[2]~reg0_q\ : std_logic;
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SIGNAL \addr_in[3]~input_o\ : std_logic;
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SIGNAL \addr_out[3]~reg0_q\ : std_logic;
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SIGNAL \addr_in[4]~input_o\ : std_logic;
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SIGNAL \addr_out[4]~reg0feeder_combout\ : std_logic;
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SIGNAL \addr_out[4]~reg0_q\ : std_logic;
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SIGNAL \addr_in[5]~input_o\ : std_logic;
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SIGNAL \addr_out[5]~reg0feeder_combout\ : std_logic;
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SIGNAL \addr_out[5]~reg0_q\ : std_logic;
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SIGNAL \addr_in[6]~input_o\ : std_logic;
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SIGNAL \addr_out[6]~reg0_q\ : std_logic;
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SIGNAL \addr_in[7]~input_o\ : std_logic;
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SIGNAL \addr_out[7]~reg0_q\ : std_logic;
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COMPONENT hard_block
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PORT (
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devoe : IN std_logic;
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devclrn : IN std_logic;
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devpor : IN std_logic);
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END COMPONENT;
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BEGIN
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ww_clk <= clk;
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ww_en_D <= en_D;
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ww_addr_in <= addr_in;
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addr_out <= ww_addr_out;
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ww_devoe <= devoe;
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ww_devclrn <= devclrn;
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ww_devpor <= devpor;
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\clk~inputclkctrl_INCLK_bus\ <= (vcc & vcc & vcc & \clk~input_o\);
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auto_generated_inst : hard_block
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PORT MAP (
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devoe => ww_devoe,
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devclrn => ww_devclrn,
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devpor => ww_devpor);
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-- Location: IOOBUF_X0_Y8_N16
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\addr_out[0]~output\ : cycloneive_io_obuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "false")
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-- pragma translate_on
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PORT MAP (
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i => \addr_out[0]~reg0_q\,
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devoe => ww_devoe,
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o => \addr_out[0]~output_o\);
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-- Location: IOOBUF_X21_Y0_N16
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\addr_out[1]~output\ : cycloneive_io_obuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "false")
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-- pragma translate_on
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PORT MAP (
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i => \addr_out[1]~reg0_q\,
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devoe => ww_devoe,
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o => \addr_out[1]~output_o\);
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-- Location: IOOBUF_X7_Y0_N2
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\addr_out[2]~output\ : cycloneive_io_obuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "false")
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-- pragma translate_on
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PORT MAP (
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i => \addr_out[2]~reg0_q\,
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devoe => ww_devoe,
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o => \addr_out[2]~output_o\);
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-- Location: IOOBUF_X0_Y10_N2
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\addr_out[3]~output\ : cycloneive_io_obuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "false")
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-- pragma translate_on
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PORT MAP (
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i => \addr_out[3]~reg0_q\,
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devoe => ww_devoe,
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o => \addr_out[3]~output_o\);
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-- Location: IOOBUF_X0_Y6_N16
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\addr_out[4]~output\ : cycloneive_io_obuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "false")
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-- pragma translate_on
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PORT MAP (
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i => \addr_out[4]~reg0_q\,
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devoe => ww_devoe,
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o => \addr_out[4]~output_o\);
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-- Location: IOOBUF_X7_Y0_N16
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\addr_out[5]~output\ : cycloneive_io_obuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "false")
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-- pragma translate_on
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PORT MAP (
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i => \addr_out[5]~reg0_q\,
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devoe => ww_devoe,
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o => \addr_out[5]~output_o\);
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-- Location: IOOBUF_X0_Y8_N23
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\addr_out[6]~output\ : cycloneive_io_obuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "false")
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-- pragma translate_on
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PORT MAP (
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i => \addr_out[6]~reg0_q\,
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devoe => ww_devoe,
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o => \addr_out[6]~output_o\);
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-- Location: IOOBUF_X7_Y0_N23
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\addr_out[7]~output\ : cycloneive_io_obuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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open_drain_output => "false")
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-- pragma translate_on
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PORT MAP (
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i => \addr_out[7]~reg0_q\,
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devoe => ww_devoe,
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o => \addr_out[7]~output_o\);
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-- Location: IOIBUF_X0_Y11_N8
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\clk~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_clk,
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o => \clk~input_o\);
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-- Location: CLKCTRL_G2
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\clk~inputclkctrl\ : cycloneive_clkctrl
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-- pragma translate_off
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GENERIC MAP (
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clock_type => "global clock",
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ena_register_mode => "none")
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-- pragma translate_on
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PORT MAP (
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inclk => \clk~inputclkctrl_INCLK_bus\,
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devclrn => ww_devclrn,
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devpor => ww_devpor,
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outclk => \clk~inputclkctrl_outclk\);
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-- Location: IOIBUF_X0_Y7_N1
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\addr_in[0]~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_addr_in(0),
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o => \addr_in[0]~input_o\);
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-- Location: LCCOMB_X1_Y7_N0
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\addr_out[0]~reg0feeder\ : cycloneive_lcell_comb
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-- Equation(s):
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-- \addr_out[0]~reg0feeder_combout\ = \addr_in[0]~input_o\
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-- pragma translate_off
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GENERIC MAP (
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lut_mask => "1111111100000000",
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sum_lutc_input => "datac")
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-- pragma translate_on
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PORT MAP (
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datad => \addr_in[0]~input_o\,
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combout => \addr_out[0]~reg0feeder_combout\);
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-- Location: IOIBUF_X0_Y9_N8
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\en_D~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_en_D,
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o => \en_D~input_o\);
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-- Location: FF_X1_Y7_N1
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\addr_out[0]~reg0\ : dffeas
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-- pragma translate_off
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GENERIC MAP (
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is_wysiwyg => "true",
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power_up => "low")
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-- pragma translate_on
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PORT MAP (
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clk => \clk~inputclkctrl_outclk\,
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d => \addr_out[0]~reg0feeder_combout\,
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ena => \en_D~input_o\,
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devclrn => ww_devclrn,
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devpor => ww_devpor,
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q => \addr_out[0]~reg0_q\);
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-- Location: IOIBUF_X0_Y7_N22
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\addr_in[1]~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_addr_in(1),
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o => \addr_in[1]~input_o\);
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-- Location: FF_X8_Y7_N9
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\addr_out[1]~reg0\ : dffeas
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-- pragma translate_off
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GENERIC MAP (
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is_wysiwyg => "true",
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power_up => "low")
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-- pragma translate_on
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PORT MAP (
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clk => \clk~inputclkctrl_outclk\,
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asdata => \addr_in[1]~input_o\,
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sload => VCC,
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ena => \en_D~input_o\,
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devclrn => ww_devclrn,
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devpor => ww_devpor,
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q => \addr_out[1]~reg0_q\);
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-- Location: IOIBUF_X9_Y0_N1
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\addr_in[2]~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_addr_in(2),
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o => \addr_in[2]~input_o\);
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-- Location: LCCOMB_X8_Y7_N2
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\addr_out[2]~reg0feeder\ : cycloneive_lcell_comb
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-- Equation(s):
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-- \addr_out[2]~reg0feeder_combout\ = \addr_in[2]~input_o\
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-- pragma translate_off
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GENERIC MAP (
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lut_mask => "1111111100000000",
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sum_lutc_input => "datac")
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-- pragma translate_on
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PORT MAP (
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datad => \addr_in[2]~input_o\,
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combout => \addr_out[2]~reg0feeder_combout\);
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-- Location: FF_X8_Y7_N3
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\addr_out[2]~reg0\ : dffeas
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-- pragma translate_off
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GENERIC MAP (
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is_wysiwyg => "true",
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power_up => "low")
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-- pragma translate_on
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PORT MAP (
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clk => \clk~inputclkctrl_outclk\,
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d => \addr_out[2]~reg0feeder_combout\,
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ena => \en_D~input_o\,
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devclrn => ww_devclrn,
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devpor => ww_devpor,
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q => \addr_out[2]~reg0_q\);
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-- Location: IOIBUF_X3_Y0_N1
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\addr_in[3]~input\ : cycloneive_io_ibuf
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-- pragma translate_off
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GENERIC MAP (
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bus_hold => "false",
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simulate_z_as => "z")
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-- pragma translate_on
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PORT MAP (
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i => ww_addr_in(3),
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o => \addr_in[3]~input_o\);
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-- Location: FF_X8_Y7_N13
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\addr_out[3]~reg0\ : dffeas
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-- pragma translate_off
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GENERIC MAP (
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is_wysiwyg => "true",
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power_up => "low")
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-- pragma translate_on
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PORT MAP (
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clk => \clk~inputclkctrl_outclk\,
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asdata => \addr_in[3]~input_o\,
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sload => VCC,
|
|
ena => \en_D~input_o\,
|
|
devclrn => ww_devclrn,
|
|
devpor => ww_devpor,
|
|
q => \addr_out[3]~reg0_q\);
|
|
|
|
-- Location: IOIBUF_X0_Y7_N15
|
|
\addr_in[4]~input\ : cycloneive_io_ibuf
|
|
-- pragma translate_off
|
|
GENERIC MAP (
|
|
bus_hold => "false",
|
|
simulate_z_as => "z")
|
|
-- pragma translate_on
|
|
PORT MAP (
|
|
i => ww_addr_in(4),
|
|
o => \addr_in[4]~input_o\);
|
|
|
|
-- Location: LCCOMB_X1_Y7_N26
|
|
\addr_out[4]~reg0feeder\ : cycloneive_lcell_comb
|
|
-- Equation(s):
|
|
-- \addr_out[4]~reg0feeder_combout\ = \addr_in[4]~input_o\
|
|
|
|
-- pragma translate_off
|
|
GENERIC MAP (
|
|
lut_mask => "1111111100000000",
|
|
sum_lutc_input => "datac")
|
|
-- pragma translate_on
|
|
PORT MAP (
|
|
datad => \addr_in[4]~input_o\,
|
|
combout => \addr_out[4]~reg0feeder_combout\);
|
|
|
|
-- Location: FF_X1_Y7_N27
|
|
\addr_out[4]~reg0\ : dffeas
|
|
-- pragma translate_off
|
|
GENERIC MAP (
|
|
is_wysiwyg => "true",
|
|
power_up => "low")
|
|
-- pragma translate_on
|
|
PORT MAP (
|
|
clk => \clk~inputclkctrl_outclk\,
|
|
d => \addr_out[4]~reg0feeder_combout\,
|
|
ena => \en_D~input_o\,
|
|
devclrn => ww_devclrn,
|
|
devpor => ww_devpor,
|
|
q => \addr_out[4]~reg0_q\);
|
|
|
|
-- Location: IOIBUF_X5_Y24_N8
|
|
\addr_in[5]~input\ : cycloneive_io_ibuf
|
|
-- pragma translate_off
|
|
GENERIC MAP (
|
|
bus_hold => "false",
|
|
simulate_z_as => "z")
|
|
-- pragma translate_on
|
|
PORT MAP (
|
|
i => ww_addr_in(5),
|
|
o => \addr_in[5]~input_o\);
|
|
|
|
-- Location: LCCOMB_X8_Y7_N30
|
|
\addr_out[5]~reg0feeder\ : cycloneive_lcell_comb
|
|
-- Equation(s):
|
|
-- \addr_out[5]~reg0feeder_combout\ = \addr_in[5]~input_o\
|
|
|
|
-- pragma translate_off
|
|
GENERIC MAP (
|
|
lut_mask => "1111111100000000",
|
|
sum_lutc_input => "datac")
|
|
-- pragma translate_on
|
|
PORT MAP (
|
|
datad => \addr_in[5]~input_o\,
|
|
combout => \addr_out[5]~reg0feeder_combout\);
|
|
|
|
-- Location: FF_X8_Y7_N31
|
|
\addr_out[5]~reg0\ : dffeas
|
|
-- pragma translate_off
|
|
GENERIC MAP (
|
|
is_wysiwyg => "true",
|
|
power_up => "low")
|
|
-- pragma translate_on
|
|
PORT MAP (
|
|
clk => \clk~inputclkctrl_outclk\,
|
|
d => \addr_out[5]~reg0feeder_combout\,
|
|
ena => \en_D~input_o\,
|
|
devclrn => ww_devclrn,
|
|
devpor => ww_devpor,
|
|
q => \addr_out[5]~reg0_q\);
|
|
|
|
-- Location: IOIBUF_X0_Y9_N1
|
|
\addr_in[6]~input\ : cycloneive_io_ibuf
|
|
-- pragma translate_off
|
|
GENERIC MAP (
|
|
bus_hold => "false",
|
|
simulate_z_as => "z")
|
|
-- pragma translate_on
|
|
PORT MAP (
|
|
i => ww_addr_in(6),
|
|
o => \addr_in[6]~input_o\);
|
|
|
|
-- Location: FF_X1_Y7_N13
|
|
\addr_out[6]~reg0\ : dffeas
|
|
-- pragma translate_off
|
|
GENERIC MAP (
|
|
is_wysiwyg => "true",
|
|
power_up => "low")
|
|
-- pragma translate_on
|
|
PORT MAP (
|
|
clk => \clk~inputclkctrl_outclk\,
|
|
asdata => \addr_in[6]~input_o\,
|
|
sload => VCC,
|
|
ena => \en_D~input_o\,
|
|
devclrn => ww_devclrn,
|
|
devpor => ww_devpor,
|
|
q => \addr_out[6]~reg0_q\);
|
|
|
|
-- Location: IOIBUF_X9_Y0_N8
|
|
\addr_in[7]~input\ : cycloneive_io_ibuf
|
|
-- pragma translate_off
|
|
GENERIC MAP (
|
|
bus_hold => "false",
|
|
simulate_z_as => "z")
|
|
-- pragma translate_on
|
|
PORT MAP (
|
|
i => ww_addr_in(7),
|
|
o => \addr_in[7]~input_o\);
|
|
|
|
-- Location: FF_X8_Y7_N1
|
|
\addr_out[7]~reg0\ : dffeas
|
|
-- pragma translate_off
|
|
GENERIC MAP (
|
|
is_wysiwyg => "true",
|
|
power_up => "low")
|
|
-- pragma translate_on
|
|
PORT MAP (
|
|
clk => \clk~inputclkctrl_outclk\,
|
|
asdata => \addr_in[7]~input_o\,
|
|
sload => VCC,
|
|
ena => \en_D~input_o\,
|
|
devclrn => ww_devclrn,
|
|
devpor => ww_devpor,
|
|
q => \addr_out[7]~reg0_q\);
|
|
|
|
ww_addr_out(0) <= \addr_out[0]~output_o\;
|
|
|
|
ww_addr_out(1) <= \addr_out[1]~output_o\;
|
|
|
|
ww_addr_out(2) <= \addr_out[2]~output_o\;
|
|
|
|
ww_addr_out(3) <= \addr_out[3]~output_o\;
|
|
|
|
ww_addr_out(4) <= \addr_out[4]~output_o\;
|
|
|
|
ww_addr_out(5) <= \addr_out[5]~output_o\;
|
|
|
|
ww_addr_out(6) <= \addr_out[6]~output_o\;
|
|
|
|
ww_addr_out(7) <= \addr_out[7]~output_o\;
|
|
END structure;
|
|
|
|
|