104 lines
4.6 KiB
Plaintext
104 lines
4.6 KiB
Plaintext
# Reading C:/intelFPGA_lite/18.0/modelsim_ase/tcl/vsim/pref.tcl
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# do 8bit_model_run_msim_rtl_vhdl.do
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# if {[file exists rtl_work]} {
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# vdel -lib rtl_work -all
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# }
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# vlib rtl_work
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# vmap work rtl_work
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# Model Technology ModelSim - Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016
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# vmap work rtl_work
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# Copying C:/intelFPGA_lite/18.0/modelsim_ase/win32aloem/../modelsim.ini to modelsim.ini
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# Modifying modelsim.ini
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#
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# vcom -93 -work work {C:/Users/Cai.MY/Desktop/8bit_model/ir.vhd}
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# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 21:12:37 on Jul 09,2018
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# vcom -reportprogress 300 -93 -work work C:/Users/Cai.MY/Desktop/8bit_model/ir.vhd
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Loading package std_logic_arith
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# -- Loading package STD_LOGIC_UNSIGNED
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# -- Compiling entity ir
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# -- Compiling architecture behav of ir
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# End time: 21:12:37 on Jul 09,2018, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# vcom -93 -work work {C:/Users/Cai.MY/Desktop/8bit_model/pc.vhd}
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# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 21:12:37 on Jul 09,2018
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# vcom -reportprogress 300 -93 -work work C:/Users/Cai.MY/Desktop/8bit_model/pc.vhd
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Loading package std_logic_arith
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# -- Loading package STD_LOGIC_UNSIGNED
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# -- Compiling entity pc
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# -- Compiling architecture behav of pc
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# End time: 21:12:38 on Jul 09,2018, Elapsed time: 0:00:01
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# Errors: 0, Warnings: 0
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# vcom -93 -work work {C:/Users/Cai.MY/Desktop/8bit_model/ar.vhd}
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# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 21:12:38 on Jul 09,2018
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# vcom -reportprogress 300 -93 -work work C:/Users/Cai.MY/Desktop/8bit_model/ar.vhd
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Loading package std_logic_arith
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# -- Loading package STD_LOGIC_UNSIGNED
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# -- Compiling entity ar
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# -- Compiling architecture behav of ar
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# End time: 21:12:38 on Jul 09,2018, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# vcom -93 -work work {C:/Users/Cai.MY/Desktop/8bit_model/ram0.vhd}
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# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 21:12:38 on Jul 09,2018
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# vcom -reportprogress 300 -93 -work work C:/Users/Cai.MY/Desktop/8bit_model/ram0.vhd
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Loading package altera_mf_components
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# -- Compiling entity ram0
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# -- Compiling architecture SYN of ram0
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# End time: 21:12:38 on Jul 09,2018, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# vcom -93 -work work {C:/Users/Cai.MY/Desktop/8bit_model/dr.vhd}
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# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 21:12:39 on Jul 09,2018
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# vcom -reportprogress 300 -93 -work work C:/Users/Cai.MY/Desktop/8bit_model/dr.vhd
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Loading package std_logic_arith
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# -- Loading package STD_LOGIC_UNSIGNED
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# -- Compiling entity dr
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# -- Compiling architecture behav of dr
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# End time: 21:12:39 on Jul 09,2018, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# vcom -93 -work work {C:/Users/Cai.MY/Desktop/8bit_model/controller.vhd}
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# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 21:12:39 on Jul 09,2018
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# vcom -reportprogress 300 -93 -work work C:/Users/Cai.MY/Desktop/8bit_model/controller.vhd
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Loading package std_logic_arith
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# -- Loading package STD_LOGIC_UNSIGNED
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# -- Compiling entity controller
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# -- Compiling architecture behav of controller
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# End time: 21:12:39 on Jul 09,2018, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# vcom -93 -work work {C:/Users/Cai.MY/Desktop/8bit_model/metronome.vhd}
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# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 21:12:39 on Jul 09,2018
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# vcom -reportprogress 300 -93 -work work C:/Users/Cai.MY/Desktop/8bit_model/metronome.vhd
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Loading package std_logic_arith
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# -- Loading package STD_LOGIC_UNSIGNED
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# -- Compiling entity metronome
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# -- Compiling architecture behav of metronome
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# End time: 21:12:39 on Jul 09,2018, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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#
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