158 lines
7.5 KiB
Plaintext
158 lines
7.5 KiB
Plaintext
Determining the location of the ModelSim executable...
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Using: C:\intelFPGA_lite\18.0\modelsim_ase\win32aloem
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To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
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Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
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**** Generating the ModelSim Testbench ****
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quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off 8bit_model -c 8bit_model --vector_source="C:/Users/Cai.MY/Desktop/8bit_model/Waveform8.vwf" --testbench_file="C:/Users/Cai.MY/Desktop/8bit_model/simulation/qsim/Waveform8.vwf.vht"
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Info: *******************************************************************
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Info: Running Quartus Prime EDA Netlist Writer
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Info: Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
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Info: Copyright (C) 2018 Intel Corporation. All rights reserved.
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Info: Your use of Intel Corporation's design tools, logic functions
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Info: and other software and tools, and its AMPP partner logic
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Info: functions, and any output files from any of the foregoing
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Info: (including device programming or simulation files), and any
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Info: associated documentation or information are expressly subject
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Info: to the terms and conditions of the Intel Program License
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Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
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Info: the Intel FPGA IP License Agreement, or other applicable license
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Info: agreement, including, without limitation, that your use is for
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Info: the sole purpose of programming logic devices manufactured by
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Info: Intel and sold by Intel or its authorized distributors. Please
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Info: refer to the applicable agreement for further details.
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Info: Processing started: Fri Jul 13 20:18:54 2018
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Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off 8bit_model -c 8bit_model --vector_source=C:/Users/Cai.MY/Desktop/8bit_model/Waveform8.vwf --testbench_file=C:/Users/Cai.MY/Desktop/8bit_model/simulation/qsim/Waveform8.vwf.vht
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Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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Completed successfully.
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**** Generating the functional simulation netlist ****
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quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="C:/Users/Cai.MY/Desktop/8bit_model/simulation/qsim/" 8bit_model -c 8bit_model
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Info: *******************************************************************
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Info: Running Quartus Prime EDA Netlist Writer
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Info: Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
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Info: Copyright (C) 2018 Intel Corporation. All rights reserved.
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Info: Your use of Intel Corporation's design tools, logic functions
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Info: and other software and tools, and its AMPP partner logic
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Info: functions, and any output files from any of the foregoing
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Info: (including device programming or simulation files), and any
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Info: associated documentation or information are expressly subject
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Info: to the terms and conditions of the Intel Program License
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Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
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Info: the Intel FPGA IP License Agreement, or other applicable license
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Info: agreement, including, without limitation, that your use is for
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Info: the sole purpose of programming logic devices manufactured by
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Info: Intel and sold by Intel or its authorized distributors. Please
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Info: refer to the applicable agreement for further details.
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Info: Processing started: Fri Jul 13 20:18:58 2018
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Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=C:/Users/Cai.MY/Desktop/8bit_model/simulation/qsim/ 8bit_model -c 8bit_model
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Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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Info (204019): Generated file 8bit_model.vho in folder "C:/Users/Cai.MY/Desktop/8bit_model/simulation/qsim//" for EDA simulation tool
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Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
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Info: Peak virtual memory: 4657 megabytes
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Info: Processing ended: Fri Jul 13 20:19:00 2018
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Info: Elapsed time: 00:00:02
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Info: Total CPU time (on all processors): 00:00:03
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Completed successfully.
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**** Generating the ModelSim .do script ****
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C:/Users/Cai.MY/Desktop/8bit_model/simulation/qsim/8bit_model.do generated.
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Completed successfully.
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**** Running the ModelSim simulation ****
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C:/intelFPGA_lite/18.0/modelsim_ase/win32aloem/vsim -c -do 8bit_model.do
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Reading C:/intelFPGA_lite/18.0/modelsim_ase/tcl/vsim/pref.tcl
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# 10.5b
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# do 8bit_model.do
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# ** Warning: (vlib-34) Library already exists at "work".
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# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:19:04 on Jul 13,2018
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# vcom -work work 8bit_model.vho
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Loading package VITAL_Timing
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# -- Loading package VITAL_Primitives
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# -- Loading package cycloneive_atom_pack
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# -- Loading package cycloneive_components
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# -- Compiling entity hard_block
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# -- Compiling architecture structure of hard_block
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# -- Loading package dffeas_pack
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# -- Loading package altera_primitives_components
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# -- Compiling entity ar
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# -- Compiling architecture structure of ar
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# End time: 20:19:04 on Jul 13,2018, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 20:19:04 on Jul 13,2018
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# vcom -work work Waveform8.vwf.vht
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Compiling entity ar_vhd_vec_tst
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# -- Compiling architecture ar_arch of ar_vhd_vec_tst
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# End time: 20:19:04 on Jul 13,2018, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# vsim -novopt -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.ar_vhd_vec_tst
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# Start time: 20:19:05 on Jul 13,2018
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# Loading std.standard
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# Loading std.textio(body)
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# Loading ieee.std_logic_1164(body)
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# Loading work.ar_vhd_vec_tst(ar_arch)
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# Loading ieee.vital_timing(body)
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# Loading ieee.vital_primitives(body)
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# Loading altera.dffeas_pack
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# Loading altera.altera_primitives_components
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# Loading cycloneive.cycloneive_atom_pack(body)
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# Loading cycloneive.cycloneive_components
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# Loading work.ar(structure)
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# Loading work.hard_block(structure)
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# Loading ieee.std_logic_arith(body)
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# Loading cycloneive.cycloneive_io_obuf(arch)
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# Loading cycloneive.cycloneive_io_ibuf(arch)
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# Loading cycloneive.cycloneive_clkctrl(vital_clkctrl)
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# Loading cycloneive.cycloneive_ena_reg(behave)
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# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
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# Loading altera.dffeas(vital_dffeas)
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# after#35
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# End time: 20:19:05 on Jul 13,2018, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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Completed successfully.
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**** Converting ModelSim VCD to vector waveform ****
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Reading C:/Users/Cai.MY/Desktop/8bit_model/Waveform8.vwf...
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Reading C:/Users/Cai.MY/Desktop/8bit_model/simulation/qsim/8bit_model.msim.vcd...
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Processing channel transitions...
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Writing the resulting VWF to C:/Users/Cai.MY/Desktop/8bit_model/simulation/qsim/8bit_model_20180713201906.sim.vwf
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Finished VCD to VWF conversion.
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Completed successfully.
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All completed. |