Determining the location of the ModelSim executable...

Using: C:\intelFPGA_lite\18.0\modelsim_ase\win32aloem

To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.

**** Generating the ModelSim Testbench ****

quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off 8bit_model -c 8bit_model --vector_source="C:/Users/Cai.MY/Desktop/8bit_model/Waveform8.vwf" --testbench_file="C:/Users/Cai.MY/Desktop/8bit_model/simulation/qsim/Waveform8.vwf.vht"

Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
    Info: Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
    Info: Copyright (C) 2018  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Fri Jul 13 20:18:54 2018
Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off 8bit_model -c 8bit_model --vector_source=C:/Users/Cai.MY/Desktop/8bit_model/Waveform8.vwf --testbench_file=C:/Users/Cai.MY/Desktop/8bit_model/simulation/qsim/Waveform8.vwf.vht
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

Completed successfully. 

**** Generating the functional simulation netlist ****

quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="C:/Users/Cai.MY/Desktop/8bit_model/simulation/qsim/" 8bit_model -c 8bit_model

Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
    Info: Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
    Info: Copyright (C) 2018  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Fri Jul 13 20:18:58 2018
Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=C:/Users/Cai.MY/Desktop/8bit_model/simulation/qsim/ 8bit_model -c 8bit_model
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file 8bit_model.vho in folder "C:/Users/Cai.MY/Desktop/8bit_model/simulation/qsim//" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 4657 megabytes
    Info: Processing ended: Fri Jul 13 20:19:00 2018
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:03

Completed successfully. 

**** Generating the ModelSim .do script ****

C:/Users/Cai.MY/Desktop/8bit_model/simulation/qsim/8bit_model.do generated.

Completed successfully. 

**** Running the ModelSim simulation ****

C:/intelFPGA_lite/18.0/modelsim_ase/win32aloem/vsim -c -do 8bit_model.do

Reading C:/intelFPGA_lite/18.0/modelsim_ase/tcl/vsim/pref.tcl


# 10.5b

# do 8bit_model.do

# ** Warning: (vlib-34) Library already exists at "work".

# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:19:04 on Jul 13,2018
# vcom -work work 8bit_model.vho 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package VITAL_Timing
# -- Loading package VITAL_Primitives
# -- Loading package cycloneive_atom_pack
# -- Loading package cycloneive_components
# -- Compiling entity hard_block

# -- Compiling architecture structure of hard_block
# -- Loading package dffeas_pack
# -- Loading package altera_primitives_components
# -- Compiling entity ar
# -- Compiling architecture structure of ar
# End time: 20:19:04 on Jul 13,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0

# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct  5 2016
# Start time: 20:19:04 on Jul 13,2018
# vcom -work work Waveform8.vwf.vht 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity ar_vhd_vec_tst
# -- Compiling architecture ar_arch of ar_vhd_vec_tst
# End time: 20:19:04 on Jul 13,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0

# vsim -novopt -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.ar_vhd_vec_tst 
# Start time: 20:19:05 on Jul 13,2018
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading work.ar_vhd_vec_tst(ar_arch)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading altera.dffeas_pack
# Loading altera.altera_primitives_components
# Loading cycloneive.cycloneive_atom_pack(body)
# Loading cycloneive.cycloneive_components
# Loading work.ar(structure)
# Loading work.hard_block(structure)
# Loading ieee.std_logic_arith(body)
# Loading cycloneive.cycloneive_io_obuf(arch)
# Loading cycloneive.cycloneive_io_ibuf(arch)
# Loading cycloneive.cycloneive_clkctrl(vital_clkctrl)
# Loading cycloneive.cycloneive_ena_reg(behave)
# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
# Loading altera.dffeas(vital_dffeas)
# after#35

# End time: 20:19:05 on Jul 13,2018, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0

Completed successfully. 

**** Converting ModelSim VCD to vector waveform ****

Reading C:/Users/Cai.MY/Desktop/8bit_model/Waveform8.vwf...

Reading C:/Users/Cai.MY/Desktop/8bit_model/simulation/qsim/8bit_model.msim.vcd...

Processing channel transitions... 

Writing the resulting VWF to C:/Users/Cai.MY/Desktop/8bit_model/simulation/qsim/8bit_model_20180713201906.sim.vwf

Finished VCD to VWF conversion.

Completed successfully. 

All completed.