60 lines
2.6 KiB
Plaintext
60 lines
2.6 KiB
Plaintext
# do 8bit_model.do
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# ** Warning: (vlib-34) Library already exists at "work".
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# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 00:43:33 on Jul 11,2018
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# vcom -work work 8bit_model.vho
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Loading package VITAL_Timing
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# -- Loading package VITAL_Primitives
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# -- Loading package cycloneive_atom_pack
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# -- Loading package cycloneive_components
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# -- Compiling entity hard_block
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# -- Compiling architecture structure of hard_block
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# -- Loading package dffeas_pack
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# -- Loading package altera_primitives_components
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# -- Compiling entity eight_bit_model
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# -- Compiling architecture structure of eight_bit_model
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# End time: 00:43:33 on Jul 11,2018, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# Model Technology ModelSim - Intel FPGA Edition vcom 10.5b Compiler 2016.10 Oct 5 2016
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# Start time: 00:43:34 on Jul 11,2018
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# vcom -work work Waveform.vwf.vht
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# -- Loading package STANDARD
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# -- Loading package TEXTIO
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# -- Loading package std_logic_1164
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# -- Compiling entity eight_bit_model_vhd_vec_tst
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# -- Compiling architecture eight_bit_model_arch of eight_bit_model_vhd_vec_tst
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# End time: 00:43:34 on Jul 11,2018, Elapsed time: 0:00:00
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# Errors: 0, Warnings: 0
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# vsim -novopt -c -t 1ps -L cycloneive -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.eight_bit_model_vhd_vec_tst
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# Start time: 00:43:34 on Jul 11,2018
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# Loading std.standard
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# Loading std.textio(body)
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# Loading ieee.std_logic_1164(body)
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# Loading work.eight_bit_model_vhd_vec_tst(eight_bit_model_arch)
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# Loading ieee.vital_timing(body)
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# Loading ieee.vital_primitives(body)
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# Loading altera.dffeas_pack
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# Loading altera.altera_primitives_components
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# Loading cycloneive.cycloneive_atom_pack(body)
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# Loading cycloneive.cycloneive_components
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# Loading work.eight_bit_model(structure)
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# Loading work.hard_block(structure)
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# Loading ieee.std_logic_arith(body)
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# Loading cycloneive.cycloneive_io_obuf(arch)
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# Loading cycloneive.cycloneive_io_ibuf(arch)
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# Loading cycloneive.cycloneive_clkctrl(vital_clkctrl)
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# Loading cycloneive.cycloneive_ena_reg(behave)
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# Loading cycloneive.cycloneive_lcell_comb(vital_lcell_comb)
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# Loading altera.dffeas(vital_dffeas)
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# Loading cycloneive.cycloneive_ram_block(block_arch)
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# Loading cycloneive.cycloneive_ram_register(reg_arch)
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# Loading cycloneive.cycloneive_ram_pulse_generator(pgen_arch)
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# ** Warning: Design size of 30669 statements exceeds ModelSim-Intel FPGA Starter Edition recommended capacity.
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# Expect performance to be adversely affected.
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# after#35
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# End time: 00:43:36 on Jul 11,2018, Elapsed time: 0:00:02
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# Errors: 0, Warnings: 1
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