90 lines
2.7 KiB
VHDL
90 lines
2.7 KiB
VHDL
-- Copyright (C) 2018 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details.
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-- *****************************************************************************
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-- This file contains a Vhdl test bench with test vectors .The test vectors
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-- are exported from a vector file in the Quartus Waveform Editor and apply to
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-- the top level entity of the current Quartus project .The user can use this
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-- testbench to simulate his design using a third-party simulation tool .
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-- *****************************************************************************
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-- Generated on "07/13/2018 15:24:24"
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-- Vhdl Test Bench(with test vectors) for design : pc
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--
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-- Simulation tool : 3rd Party
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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ENTITY pc_vhd_vec_tst IS
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END pc_vhd_vec_tst;
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ARCHITECTURE pc_arch OF pc_vhd_vec_tst IS
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-- constants
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-- signals
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SIGNAL clk : STD_LOGIC;
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SIGNAL clr : STD_LOGIC;
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SIGNAL en_D : STD_LOGIC;
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SIGNAL pc_out : STD_LOGIC_VECTOR(7 DOWNTO 0);
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COMPONENT pc
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PORT (
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clk : IN STD_LOGIC;
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clr : IN STD_LOGIC;
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en_D : IN STD_LOGIC;
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pc_out : BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0)
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);
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END COMPONENT;
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BEGIN
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i1 : pc
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PORT MAP (
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-- list connections between master ports and signals
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clk => clk,
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clr => clr,
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en_D => en_D,
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pc_out => pc_out
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);
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-- clk
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t_prcs_clk: PROCESS
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BEGIN
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LOOP
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clk <= '0';
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WAIT FOR 5000 ps;
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clk <= '1';
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WAIT FOR 5000 ps;
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IF (NOW >= 1000000 ps) THEN WAIT; END IF;
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END LOOP;
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END PROCESS t_prcs_clk;
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-- clr
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t_prcs_clr: PROCESS
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BEGIN
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clr <= '0';
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WAIT FOR 100000 ps;
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clr <= '1';
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WAIT FOR 70000 ps;
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clr <= '0';
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WAIT;
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END PROCESS t_prcs_clr;
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-- en_D
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t_prcs_en_D: PROCESS
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BEGIN
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en_D <= '0';
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WAIT FOR 60000 ps;
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en_D <= '1';
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WAIT;
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END PROCESS t_prcs_en_D;
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END pc_arch;
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