8bit_model/simulation/qsim/8bit_model.msim.vcd

$comment
	File created using the following command:
		vcd file 8bit_model.msim.vcd -direction
$end
$date
	Fri Jul 13 20:19:05 2018
$end
$version
	ModelSim Version 10.5b
$end
$timescale
	1ps
$end

$scope module ar_vhd_vec_tst $end
$var wire 1 ! addr_in [7] $end
$var wire 1 " addr_in [6] $end
$var wire 1 # addr_in [5] $end
$var wire 1 $ addr_in [4] $end
$var wire 1 % addr_in [3] $end
$var wire 1 & addr_in [2] $end
$var wire 1 ' addr_in [1] $end
$var wire 1 ( addr_in [0] $end
$var wire 1 ) addr_out [7] $end
$var wire 1 * addr_out [6] $end
$var wire 1 + addr_out [5] $end
$var wire 1 , addr_out [4] $end
$var wire 1 - addr_out [3] $end
$var wire 1 . addr_out [2] $end
$var wire 1 / addr_out [1] $end
$var wire 1 0 addr_out [0] $end
$var wire 1 1 clk $end
$var wire 1 2 en_D $end

$scope module i1 $end
$var wire 1 3 gnd $end
$var wire 1 4 vcc $end
$var wire 1 5 unknown $end
$var wire 1 6 devoe $end
$var wire 1 7 devclrn $end
$var wire 1 8 devpor $end
$var wire 1 9 ww_devoe $end
$var wire 1 : ww_devclrn $end
$var wire 1 ; ww_devpor $end
$var wire 1 < ww_clk $end
$var wire 1 = ww_en_D $end
$var wire 1 > ww_addr_in [7] $end
$var wire 1 ? ww_addr_in [6] $end
$var wire 1 @ ww_addr_in [5] $end
$var wire 1 A ww_addr_in [4] $end
$var wire 1 B ww_addr_in [3] $end
$var wire 1 C ww_addr_in [2] $end
$var wire 1 D ww_addr_in [1] $end
$var wire 1 E ww_addr_in [0] $end
$var wire 1 F ww_addr_out [7] $end
$var wire 1 G ww_addr_out [6] $end
$var wire 1 H ww_addr_out [5] $end
$var wire 1 I ww_addr_out [4] $end
$var wire 1 J ww_addr_out [3] $end
$var wire 1 K ww_addr_out [2] $end
$var wire 1 L ww_addr_out [1] $end
$var wire 1 M ww_addr_out [0] $end
$var wire 1 N \clk~inputclkctrl_INCLK_bus\ [3] $end
$var wire 1 O \clk~inputclkctrl_INCLK_bus\ [2] $end
$var wire 1 P \clk~inputclkctrl_INCLK_bus\ [1] $end
$var wire 1 Q \clk~inputclkctrl_INCLK_bus\ [0] $end
$var wire 1 R \addr_out[0]~output_o\ $end
$var wire 1 S \addr_out[1]~output_o\ $end
$var wire 1 T \addr_out[2]~output_o\ $end
$var wire 1 U \addr_out[3]~output_o\ $end
$var wire 1 V \addr_out[4]~output_o\ $end
$var wire 1 W \addr_out[5]~output_o\ $end
$var wire 1 X \addr_out[6]~output_o\ $end
$var wire 1 Y \addr_out[7]~output_o\ $end
$var wire 1 Z \clk~input_o\ $end
$var wire 1 [ \clk~inputclkctrl_outclk\ $end
$var wire 1 \ \addr_in[0]~input_o\ $end
$var wire 1 ] \addr_out[0]~reg0feeder_combout\ $end
$var wire 1 ^ \en_D~input_o\ $end
$var wire 1 _ \addr_out[0]~reg0_q\ $end
$var wire 1 ` \addr_in[1]~input_o\ $end
$var wire 1 a \addr_out[1]~reg0_q\ $end
$var wire 1 b \addr_in[2]~input_o\ $end
$var wire 1 c \addr_out[2]~reg0feeder_combout\ $end
$var wire 1 d \addr_out[2]~reg0_q\ $end
$var wire 1 e \addr_in[3]~input_o\ $end
$var wire 1 f \addr_out[3]~reg0_q\ $end
$var wire 1 g \addr_in[4]~input_o\ $end
$var wire 1 h \addr_out[4]~reg0feeder_combout\ $end
$var wire 1 i \addr_out[4]~reg0_q\ $end
$var wire 1 j \addr_in[5]~input_o\ $end
$var wire 1 k \addr_out[5]~reg0feeder_combout\ $end
$var wire 1 l \addr_out[5]~reg0_q\ $end
$var wire 1 m \addr_in[6]~input_o\ $end
$var wire 1 n \addr_out[6]~reg0_q\ $end
$var wire 1 o \addr_in[7]~input_o\ $end
$var wire 1 p \addr_out[7]~reg0_q\ $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
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$end
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